Current Mode PWM Boost Converter Frequency Dithering
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Solution Overview
Problem
Conventional DC-DC converters using the Spread Spectrum Frequency Dithering (SSFD) technique face challenges in maintaining voltage regulation characteristics when switching frequencies change, leading to voltage ripples and inefficiencies due to variations in inductor current and duty ratios.
Innovation Solution
A current mode PWM boost converter is designed with a pseudo random clock generating unit that varies the clock signal frequency, a reset signal generating circuit that adjusts the activation time based on the frequency variation, and a feedback signal generating circuit that compensates for slope changes in the slope compensation ramp signal, maintaining the duty ratio and stabilizing the output voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the clock signal frequency is varied using SSFD technique, then electromagnetic interference is reduced, but voltage regulation characteristics deteriorate and voltage ripples increase
Solution Approach 1:
The reset signal generating circuit performs preliminary action by adjusting the activation time of the reset signal based on the clock frequency variation before the duty ratio can drift. This proactive adjustment prevents voltage regulation deterioration rather than correcting it after occurrence
Solution Approach 2:
The system implements feedback by continuously monitoring the clock frequency and using this information to adjust the reset signal activation time. The reset signal generating circuit receives the clock signal and uses its frequency information to dynamically control the duty ratio, creating a closed-loop control mechanism that maintains voltage regulation under frequency variation
2Object-affected harmful factors
If the clock signal frequency changes, then frequency dithering effect is achieved, but duty ratio stability is compromised
Solution Approach 1:
The reset signal generating circuit adjusts the activation time of the reset signal in advance based on the detected clock frequency, preventing duty ratio instability before it occurs. This preliminary adjustment ensures that the duty ratio remains stable despite frequency dithering
Solution Approach 2:
The system changes the parameter of reset signal activation time dynamically according to the clock frequency. By varying this timing parameter in response to frequency changes, the system maintains optimal duty ratio stability across different operating frequencies
3Object-affected harmful factors
If frequency dithering is applied, then noise distribution is improved, but voltage ripple increases
Solution Approach 1:
The reset signal generating circuit uses feedback from the clock frequency to dynamically adjust the reset signal timing, creating a control mechanism that counteracts the voltage ripple generation caused by frequency dithering while preserving the noise distribution benefits
Data Source
AI summary
A current mode PWM converter configured to maintain a duty ratio of a driving signal for driving a boost circuit boosting an input voltage to an output voltage when a frequency of a clock signal for generating the driving signal is varied.