PWM Circuit Layout for Stable Pulses Without Phase Splitters
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Solution Overview
Problem
Existing semiconductor devices face challenges in generating constant pulse signals when duty variations occur in clock signals, and they often require phase splitters to manage phase differences between clock signals.
Innovation Solution
A semiconductor device is designed with a plurality of pulse width modulation circuits that include inverters and NOR gates, allowing for the generation of constant pulse signals without the need for a phase splitter. The device ensures that there are no overlapping or floating sections between clock signals, maintaining consistent pulse widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase splitters are used to manage phase differences between clock signals, then phase difference management is improved, but device complexity increases
Solution Approach 1:
The patent removes the phase splitter component from the circuit architecture entirely. Instead of using a phase splitter to generate phase-shifted clock signals, the invention directly uses the original clock signal and its inverted version to drive the pulse width modulation circuits, thereby eliminating the source of phase-related complexity while maintaining reliable phase difference management through the inherent symmetry of the circuit design.
Solution Approach 2:
The pulse width modulation circuits are designed to handle multiple functions without requiring separate phase management components. The same circuit structure processes both the original clock signal and the phase-inverted clock signal, generating corresponding output signals that inherently maintain the required phase relationships through the circuit's symmetric design rather than through dedicated phase management hardware.
2Device complexity
If duty variations occur in clock signals, then pulse signal stability deteriorates, but circuit simplicity is maintained
Solution Approach 1:
The patent employs parameter changes by utilizing both the original clock signal and its inverted version as input signals to the pulse width modulation circuits. This dual-input approach with complementary phase relationships ensures that when duty variations occur in one signal, the other signal compensates for these variations, thereby maintaining stable pulse signal generation without requiring complex compensation circuits.
Solution Approach 2:
The circuit incorporates inherent feedback mechanisms through the symmetric arrangement of pulse width modulation circuits that process complementary clock signals. The output signals from these circuits are designed to compensate for duty cycle variations in the input clock signals, effectively using the relationship between the original and inverted clock signals to maintain pulse stability without external feedback control.
3Ease of operation
If overlapping or floating sections occur between clock signals, then data quality deteriorates, but circuit operation is simplified
Solution Approach 1:
The patent uses asymmetric timing relationships between the original clock signal and its inverted version to prevent overlapping and floating sections in the output pulse signals. By designing the pulse width modulation circuits to respond to the complementary edges of these asymmetric clock signals, the invention ensures that output signals from adjacent circuits are properly timed and do not overlap, thereby maintaining high data quality through deliberate asymmetric timing design rather than complex synchronization mechanisms.
Data Source
AI summary
A semiconductor device includes a plurality of pulse width modulation circuits, wherein the respective pulse width modulation circuits include a first inverter for inverting clock signals and outputting a first inversion signal, a NOR gate for performing a NOR operation on the first inversion signal and a first logic signal and outputting a second logic signal, and a second inverter for inverting the second logic signal and outputting a second inversion signal. Regarding two adjacent pulse width modulation circuits from among the pulse width modulation circuits, a clock signal of one pulse width modulation circuit is delayed from a clock signal of the other pulse width modulation circuit from among the pulse width modulation circuits by a predetermined phase, and the first logic signal of the one pulse width modulation circuit is the second logic signal of the other pulse width modulation circuit.