PWM Clock Generation Circuit for Voltage Regulator Transient Response
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Solution Overview
Problem
Voltage regulators face challenges in improving transient response and reducing time delay while minimizing output capacitance, leading to conflicts between high frequency response and middle frequency voltage dynamic regulation, which results in increased system costs and potential output voltage overshoot.
Innovation Solution
The implementation of a PWM clock generation circuit that includes a current circuit and filter circuit to reduce PWM pulse delay during load step transients, bypassing the compensation circuit's bandwidth delay and modifying the window voltage to prevent output voltage overshoot, thereby maintaining proper duty cycle without additional cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the output capacitance of the voltage regulator is reduced, then the system cost is reduced, but the transient response time is increased
Solution Approach 1:
The patent applies preliminary action by detecting the load transient condition before the voltage regulator responds, and提前 generating a delayed PWM clock signal to accelerate the response. The transient detection circuit monitors the output voltage and提前 triggers the clock signal adjustment, allowing the system to react faster without requiring larger output capacitance.
2Speed
If the compensation circuit bandwidth is increased to improve transient response, then the transient response is improved, but the output voltage overshoot increases
Solution Approach 1:
The patent applies dynamics by making the PWM clock signal timing dynamic rather than fixed. The system adjusts the PWM clock signal delay based on the detected transient condition, using a delayed clock signal during transients to accelerate response while returning to normal timing during steady state, thus avoiding continuous overshoot issues associated with high bandwidth compensation.
3Loss of time
If the PWM pulse delay is reduced to improve transient response, then the transient response is improved, but the duty cycle control accuracy is degraded
Solution Approach 1:
The patent applies segmentation by separating the PWM clock signal generation into two paths: a normal path for steady-state operation that maintains accurate duty cycle control, and a transient acceleration path that generates a delayed PWM clock signal to reduce pulse delay during transients. The system switches between these paths based on transient detection, thus achieving both accurate normal operation and fast transient response.
Data Source
AI summary
A pulse control clock generator for a voltage regulator including a comparator, a window circuit, a filter circuit, a ramp circuit, and a current circuit. The comparator compares a ramp voltage with a compensation voltage and provides a corresponding pulse control signal. The compensation voltage is indicative of output voltage error. The window circuit adds a window voltage to the compensation voltage to provide a hysteretic voltage. The filter circuit filters the hysteretic voltage to provide a filtered hysteretic voltage, such that a difference between the compensation voltage and the filtered hysteretic voltage is reduced in response to a load increase. The ramp circuit provides a repetitive ramp voltage which ramps between the filtered hysteretic voltage and the compensation voltage based on the pulse control signal. The current circuit increases a slope of the ramp voltage in response to the load increase.