PWM Clock Demodulation for IC Synchronization Without SYSREF
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Solution Overview
Problem
Existing methods for synchronizing semiconductor IC chips using additional clock synchronization signals, such as SYSREF or PPS, are hardware-intensive and face challenges with increasing reference clock frequencies, requiring additional components and power, and can lead to communication errors due to asynchronous power-up sequences.
Innovation Solution
A demodulation circuit that embeds synchronization signals within the reference clock by pulse-width modulation, allowing IC chips to detect transitions and generate synchronized output clocks using an edge detector, modulation detection circuit, retiming circuit, and multiplexor, reducing the need for additional hardware and improving synchronization accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional clock synchronization signals (SYSREF, PPS) are used to synchronize IC chips, then synchronization accuracy is improved, but device complexity and hardware requirements increase
Solution Approach 1:
The patent combines the clock signal and synchronization information into a single pulse-width modulated clock signal. The duty cycle of the clock signal carries synchronization data, eliminating the need for separate synchronization channels and reducing hardware complexity while maintaining synchronization accuracy.
Solution Approach 2:
The clock signal serves multiple functions simultaneously: it provides the timing reference for IC chips and embeds synchronization information through pulse-width modulation. This multi-functionality reduces the number of required components and simplifies the overall system architecture.
2Reliability
If additional clock synchronization signals are used, then synchronization capability is improved, but power consumption increases
Solution Approach 1:
By merging synchronization information into the existing clock signal through pulse-width modulation, the patent eliminates the need for additional power-hungry synchronization circuits and signal paths, thereby reducing overall power consumption while maintaining synchronization capability.
3Ease of manufacture
If traditional synchronization methods are used, then hardware implementation is straightforward, but communication errors occur due to asynchronous power-up sequences
Solution Approach 1:
The pulse-width modulated clock signal provides synchronization information that enables IC chips to align their timing before normal communication begins. This preliminary synchronization ensures that even with asynchronous power-up sequences, the chips are properly synchronized before data transmission starts, preventing communication errors.
Data Source
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Figure 3A~3B
AI summary
A demodulator for pulse-width modulated clock signals is disclosed. In one aspect, the demodulator includes an edge detector configured to detect transitions in a reference clock and output a signal indicative of timing of the detected transitions. The demodulator may also include a modulation detection circuit configured to identify modulation events of at least one pulse-width modulated pulse in the reference clock based on the signal output from the edge detector and output a signal indicative of the at least one pulse-width modulated pulse modulation event being identified. The demodulator may further include a retiming circuit configured to generate an output clock synchronized with the at least one pulse-width modulated pulse modulation event based on the signal output from the modulation detection circuit.