PWM Clock Line Embedding ToD Synchronization
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Solution Overview
Problem
Existing network communication systems face challenges in maintaining synchronization of Time of Day (ToD) counters across line cards due to process, voltage, and temperature (PVT) variations, leading to continuous time errors (CTE).
Innovation Solution
The proposed solution involves using a pulse width modulated (PWM) clock signal to embed control words and data, including time of day information, directly into the clock signal line. This method allows for the synchronization of ToD counters and reduces CTE by aligning the local clocks with the network time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional separate communication channels are used for timing signals and data, then timing synchronization can be maintained, but additional communication infrastructure and complexity are required
Solution Approach 1:
The patent combines timing signals and data communication into a single clock signal line using pulse width modulation. The clock signal carrier conveys both timing information and modulated data, eliminating the need for separate communication channels and reducing overall system complexity while maintaining synchronization reliability
Solution Approach 2:
The clock signal line serves multiple functions simultaneously: it provides timing synchronization, carries modulated data, and enables bidirectional communication. This multi-functionality reduces the number of dedicated infrastructure components needed while maintaining all required communication capabilities
2Adaptability or versatility
If pulse width modulation is used to embed data in clock signal, then existing clock infrastructure can be utilized for data communication, but the clock signal processing complexity increases
Solution Approach 1:
The system uses the existing clock signal infrastructure to carry both timing and data functions without requiring external modulation equipment. The clock signal itself serves as the carrier, and the PWM encoding/decoding is performed within the timing synchronization system, making the system self-sufficient and reducing external complexity
Solution Approach 2:
The patent changes the duty cycle parameter of the clock signal to encode data information. By varying the pulse width (duty cycle) of the clock signal, data is embedded in the timing signal itself, allowing existing clock infrastructure to handle both timing and communication functions
3Productivity
If bidirectional communication is implemented over the clock line, then communication efficiency improves, but signal interference and synchronization challenges increase
Solution Approach 1:
The patent uses periodic beacon signals transmitted at regular intervals to maintain synchronization and enable bidirectional communication. These periodic beacons provide reference points for timing alignment and allow the system to maintain reliable synchronization even with bidirectional traffic on the same channel
Solution Approach 2:
The system implements feedback mechanisms where receiving devices send acknowledgments and status information back to the transmitting device through the same clock line. This feedback enables error detection, retransmission protocols, and dynamic adjustment of communication parameters to maintain reliability despite bidirectional signal interactions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of PWM clock signals effectively reduces continuous time errors (CTE) by ensuring precise synchronization of ToD counters across line cards, even under PVT variations, thereby enhancing the accuracy and reliability of network communications.
Implementation Method 1
A pulse width modulation circuit modulates periods of the clock signal according to information to be transmitted to thereby generate a pulse width modulated clock signal
Data Source
AI summary
A system includes a plurality of line cards and a timing card. A clock generation circuit on the timing card generates a clock signal which is pulse width modulated according to information to be transmitted. A clock line supplies the pulse width modulated clock signal to the line cards. The timing card sends a first control word to the plurality of line cards over the clock line after sending a beacon. The first control word includes a size field specifying a first length of first data following the first control word. The timing card sends time of day information over the clock line to the line cards following the first control word. The time of day information may be encrypted. A second control word follows the time of day information. One or more additional control words can follow the second control word before the next beacon.