PWM Clock Distribution With Phase Offset Correction

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Solution Overview

Problem

Current network systems face challenges in achieving accurate clock signal distribution due to inherent errors in existing methods, which fail to meet the precise timing requirements of modern networks, especially in systems like synchronized Ethernet and precision time protocol clocks.

Innovation Solution

The method involves receiving multiple clock signals, determining frequency and phase offset data, and transmitting these on a pulse-width modulated clock signal to enable precise recovery and synchronization across the network, correcting for quantization errors by periodic phase offset measurements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If current clock distribution methods are used, then the system is simple to implement, but the clock signal accuracy is insufficient to meet precise timing requirements

Engineering Contradiction:
Improveclock signal accuracyVSAvoiddistribution system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements feedback mechanisms where phase offset data is periodically measured and transmitted back to the transmitting device. The receiving device compares receiver phase offset data with transmitted phase offset data to generate frequency offset adjustments, which are then fed back to correct the clock signals. This closed-loop feedback system continuously refines clock accuracy while managing system complexity through automated correction processes.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent replaces traditional mechanical or simple electronic clock distribution mechanisms with a digital signal processing approach using pulse-width modulation (PWM) to encode and transmit frequency and phase offset data. This substitution enables precise digital measurement and correction of clock signals, achieving high accuracy through software-based frequency offset adjustment rather than relying solely on hardware precision.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If frequency offset data is transmitted continuously, then the clock accuracy is maintained, but the data transmission bandwidth is consumed

Engineering Contradiction:
Improvefrequency offset accuracyVSAvoidbandwidth consumption
Core Design Contradiction:
Measurement precisionVSLoss of information

Solution Approach 1:

The patent employs periodic action by transmitting phase offset data at specific intervals rather than continuously. The system periodically measures phase offsets between clock signals and transmits this data only when necessary for correction. This periodic transmission maintains clock accuracy while significantly reducing bandwidth consumption compared to continuous data transmission, as the system updates frequency offset adjustments only when phase drift exceeds acceptable thresholds.

Inventive Principle:
Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures accurate clock signal distribution with reduced errors, meeting the stringent timing requirements of modern networks by using differential timing methods augmented with periodic phase offset corrections.

Implementation Method 1

transmitting the first clock signal, the frequency offset data, and the phase offset data on a pulse-width modulated clock signal

Methodology Applied
Scientific EffectPulse-width modulation: Phase Modulation

Data Source

PatentUS11372441B2Zero offset clock distribution
Publication Date: 2022.06.28 RENESAS ELECTRONICS AMERICA INC
  • US11372441B2 patent drawing
  • US11372441B2 patent drawing

AI summary

A method of distributing clock signals includes receiving a plurality of clock signals into a corresponding plurality of processing blocks; determining frequency offset data between a first clock signal of the plurality of clock signals and each of the other clock signals of the plurality of clock signals; periodically determining phase offset data between the first clock signal and the other clock signals; and transmitting the first clock signal, the frequency offset data, and the phase offset data on a pulse-width modulated clock signal. The method includes receiving a modulated clock signal, the modulated clock signal include a carrier clock signal, a frequency offset data, and a phase offset data on a pulse-width modulated clock signal; and recovering a plurality of clock signals based on the first clock signal, the frequency offset data, and the phase offset data.