PWM Clock Demodulation for IC Synchronization Without SYSREF
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Solution Overview
Problem
Existing methods for synchronizing semiconductor IC chips using additional clock synchronization signals, such as SYSREF or PPS, are hardware-intensive and face challenges with increasing reference clock frequencies, requiring additional components and power, and are inefficient in retiming the reference clock.
Innovation Solution
A demodulation circuit that embeds synchronization signals on the reference clock by pulse-width modulation, allowing IC chips to detect transitions and generate an output clock synchronized with pulse-width modulated pulses, reducing the need for additional hardware and improving synchronization efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional clock synchronization signals (SYSREF, PPS) are used to synchronize IC chips, then synchronization accuracy is improved, but device complexity and hardware requirements increase
Solution Approach 1:
The patent combines the clock signal and synchronization information into a single pulse-width modulated clock signal. The width of each clock pulse encodes synchronization timing information, eliminating the need for separate synchronization signals like SYSREF or PPS. This merging reduces hardware complexity while maintaining synchronization accuracy through the pulse width encoding mechanism.
Solution Approach 2:
The reference clock signal serves multiple functions simultaneously: it provides the timing reference for IC chip operation and embeds synchronization information through pulse-width modulation. This multi-functionality eliminates the need for additional dedicated synchronization hardware, reducing device complexity while maintaining precise synchronization capability.
2Reliability
If additional clock synchronization signals are used, then synchronization capability is improved, but power consumption increases
Solution Approach 1:
By merging synchronization information into the existing clock signal through pulse-width modulation, the patent eliminates the need for additional synchronization signal paths and associated power consumption. The same clock signal that drives the IC chips also carries synchronization timing, reducing overall power usage while maintaining reliable synchronization capability.
3Speed
If traditional retiming methods are used for high frequency reference clocks, then clock distribution is achieved, but synchronization efficiency deteriorates
Solution Approach 1:
The synchronization information is embedded in advance into the clock signal through pulse-width modulation at the source. This preliminary encoding allows receiving IC chips to directly extract synchronization timing from the incoming clock signal without requiring complex retiming operations, thereby maintaining high synchronization efficiency even at elevated clock frequencies.
Data Source
AI summary
A demodulator for pulse-width modulated clock signals is disclosed. In one aspect, the demodulator includes an edge detector configured to detect transitions in a reference clock and output a signal indicative of timing of the detected transitions. The demodulator may also include a modulation detection circuit configured to identify modulation events of at least one pulse-width modulated pulse in the reference clock based on the signal output from the edge detector and output a signal indicative of the at least one pulse-width modulated pulse modulation event being identified. The demodulator may further include a retiming circuit configured to generate an output clock synchronized with the at least one pulse-width modulated pulse modulation event based on the signal output from the modulation detection circuit.