Configurable Time Delays for PWM Signal Synchronization
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Solution Overview
Problem
In power conversion applications, non-uniform PWM signal path delays due to different isolators, gate drivers, and power transistors result in poor timing control, increased transistor stress, and reduced reliability and efficiency.
Innovation Solution
Configurable time delay circuits are introduced to synchronize PWM control signals, with each delay setting determined based on the maximum propagation time, ensuring all signals arrive at power transistors simultaneously, thereby minimizing timing discrepancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If PWM signal path components (isolators, gate drivers, power transistors) are used with different inherent delays, then the power conversion circuit can operate with standard components, but the PWM control timing becomes non-uniform causing shoot-through and voltage spikes
Solution Approach 1:
The patent introduces configurable delay circuits that adjust the PWM signal timing parameters to compensate for the inherent delay differences in various components. By measuring and adjusting delay times for each PWM signal path, the system achieves uniform timing control while using standard off-the-shelf components like isolators, gate drivers, and power transistors with varying characteristics.
2Productivity
If PWM switching frequency is increased to shrink power conversion circuit size, then the power conversion efficiency improves, but the constant PWM signal delays become a larger portion of the PWM cycle increasing transistor stress
Solution Approach 1:
The patent implements dynamic delay adjustment where the delay circuit configuration can be adapted to different PWM switching frequencies. As the switching frequency increases and the PWM cycle shortens, the delay compensation is optimized to ensure that the delayed PWM signals still arrive at the correct timing, preventing excessive transistor stress while maintaining the benefits of high-frequency operation for reduced circuit size.
3Device complexity
If PWM signal path delays are not compensated, then the circuit design is simpler, but the power conversion efficiency decreases due to poor timing control
Solution Approach 1:
The patent implements a self-measuring and self-adjusting delay compensation system. The delay measurement circuit automatically measures the delay times in each PWM signal path, and the delay adjustment circuits automatically adjust the timing based on these measurements. This self-service approach minimizes manual calibration complexity while achieving the timing precision needed for high power conversion efficiency.
Data Source
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AI summary
A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.