PWM Counter Synchronization With Offset Reset for Distributed Drives
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Solution Overview
Problem
Distributed control systems, such as those in industrial drive systems, face desynchronization issues due to clock drift, generation errors, and propagation differences, which affect the coordinated operation of motors and actuators across a network.
Innovation Solution
A synchronized pulse width modulation (PWM) system using an initiator and receiver module with hardware-based synchronization, where a synchronization frame is transmitted over a bidirectional interconnect to reset the receiver PWM count with an offset, ensuring deterministic and accurate synchronization of PWM counts across devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If distributed controllers use identical clock timing to maintain synchronization, then coordination between motors and actuators is achieved, but clock drift and propagation differences cause desynchronization over time
Solution Approach 1:
The system implements a feedback mechanism where a primary controller generates synchronization frames that are transmitted to secondary controllers. Each synchronization frame contains timing information that allows secondary controllers to adjust their PWM counts based on actual transmission and reception timing, compensating for clock drift and propagation delays through continuous feedback correction
Solution Approach 2:
The system performs preliminary synchronization by resetting PWM counts to predetermined values at the beginning of each synchronization frame period. This preliminary action establishes a known reference point before control operations begin, preventing drift accumulation by periodically re-synchronizing all controllers to the same reference timing
2Measurement precision
If hardware-based synchronization with offset correction is implemented, then synchronization accuracy within a single PWM clock cycle is achieved, but system complexity increases
Solution Approach 1:
The system introduces a bidirectional interconnect as an intermediary communication channel between primary and secondary controllers. This interconnect transmits synchronization frames containing timing information and offset corrections, serving as a mediator that enables precise synchronization without requiring complex direct controller-to-controller coordination logic
Solution Approach 2:
The system changes the parameter of PWM count by resetting it to a predetermined value plus an offset at the beginning of each synchronization frame. This parameter change approach allows precise synchronization by adjusting the starting point of PWM counting based on measured transmission delays, achieving high precision through simple parameter adjustment rather than complex timing logic
3Adaptability or versatility
If software-based synchronization is used, then implementation flexibility is maintained, but synchronization accuracy and determinism are reduced
Solution Approach 1:
The system replaces software-based synchronization with a hardware-based approach where synchronization frames are generated and processed through hardware logic. This substitution eliminates software timing uncertainties and CPU-dependent variations, providing deterministic synchronization while maintaining adaptability through configurable offset values and synchronization frame formats
Data Source
AI summary
In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.