PWM Counter Circuit with Register Swapping for Asymmetrical Outputs
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Solution Overview
Problem
Conventional counter circuits require more registers and comparators to generate pulse width modulated signals, leading to increased power consumption and inefficiency in controlling switching mode power supplies, especially when managing asymmetrical commands for high side and low side driver circuits.
Innovation Solution
A counter circuit design featuring two pairs of registers that swap contents based on timer overflow or underflow conditions, coupled with a waveform generator and demultiplexing circuit, allows for the generation of composite pulse width modulated signals with specified periods and duty cycles using fewer registers and comparators, reducing power consumption and enabling efficient control of switching mode power supplies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional counter circuits use separate registers and comparators for each pulse width modulated signal, then signal generation capability is achieved, but device complexity and power consumption increase
Solution Approach 1:
The patent combines two separate pulse width modulated signal generation functions into a single counter circuit that uses shared registers and comparators. The counter circuit generates both PWM signals by selectively enabling output channels based on timer overflow/underflow conditions, thereby reducing the total number of registers and comparators needed while maintaining full signal generation capability
Solution Approach 2:
The counter circuit is designed to perform multiple functions using a single set of registers and comparators. It can generate two different pulse width modulated signals with independent duty cycles and frequencies by utilizing a demultiplexing circuit that distributes the single counter output to multiple output channels, making the circuit universal and reducing overall complexity
2Use of energy by stationary object
If conventional counter circuits use more registers and comparators, then signal generation accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent merges multiple signal generation functions into a single counter circuit with shared registers and comparators, reducing the number of active components and thereby lowering power consumption. The circuit maintains precision by using a demultiplexing approach where a single high-precision counter output is distributed to multiple channels with independent duty cycle control
Solution Approach 2:
The counter circuit uses periodic timer overflow and underflow events to trigger register swapping and waveform generation. This periodic action allows the circuit to maintain accurate duty cycle and frequency specifications through timed operations rather than requiring continuous high-power operation of multiple separate components
Data Source
AI summary
A counter circuit includes two pairs of registers configured to swap contents based on a timer overflow or underflow condition. The counter circuit also includes a waveform generator that generates a composite pulse width modulated signal with a period and duty cycle specified by values stored in the registers. A demultiplexing circuit generates first and second signals from the composite signal.