PWM Synchronization Circuit With Counter Reset for Smaller IC Area

The patent combines the phase-locked loop clock generating circuit, counter circuit, and comparison circuit into a single integrated PWM signal control device. The phase-locked loop circuit generates a clock signal that is fed to the counter circuit, which counts the clock signals and outputs a count value to the comparison circuit. This integration eliminates the need for separate external components and reduces overall circuit area while maintaining functionality.

The counter circuit serves multiple functions: it counts the phase-locked loop clock signals, generates a count value for PWM duty cycle control, and provides timing synchronization for the comparison circuit. The phase-locked loop clock generating circuit simultaneously provides clock signals for counting and synchronization references, reducing the need for separate timing circuits.

The PWM signal control device is segmented into three functional modules: a phase-locked loop clock generating circuit for clock signal generation, a counter circuit for counting and duty cycle control, and a comparison circuit for PWM signal generation. This segmentation allows each module to be optimized for its specific function while being integrated into a compact design suitable for IC fabrication.

The counter circuit uses a programmable count threshold that can be adjusted to change the PWM duty cycle. By changing the count threshold parameter, the device can adapt to different PWM requirements without requiring additional hardware components, maintaining versatility while keeping the circuit area small.