PWM Counter Synchronization Using Hardware Reset Offsets
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Solution Overview
Problem
Distributed control systems, such as those in industrial drive systems, face desynchronization issues due to clock drift, generation errors, and propagation differences, which affect the coordinated operation of motors and actuators across a network.
Innovation Solution
A synchronized pulse width modulation (PWM) system using an initiator and receiver module, where the initiator generates a synchronization pulse and frame, and the receiver resets its count with an offset to align with the initiator's count, utilizing a hardware layer for deterministic synchronization, independent of software-related delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If distributed controllers use identical clock timing to maintain synchronization, then coordination between motors and actuators is achieved, but clock drift and propagation differences cause desynchronization over time
Solution Approach 1:
The patent implements a feedback mechanism where a primary PWM controller generates synchronization pulses that are transmitted to secondary PWM controllers. The secondary controllers receive these pulses and adjust their PWM counts accordingly, creating a closed-loop feedback system that continuously corrects for clock drift and propagation differences, thereby maintaining synchronization accuracy despite time loss issues
Solution Approach 2:
The primary PWM controller performs preliminary action by generating and transmitting synchronization pulses before the secondary controllers can drift out of sync. This proactive synchronization approach prevents accumulation of timing errors by continuously resetting the timing reference across all distributed controllers
2Adaptability or versatility
If software-based synchronization methods are used, then implementation flexibility is achieved, but software-induced delays reduce synchronization precision
Solution Approach 1:
The patent replaces software-based synchronization with a hardware-based approach using dedicated PWM controllers and hardware timing circuits. The primary controller generates synchronization pulses through hardware logic, and secondary controllers use hardware timers and counters to receive and process these pulses, eliminating software-induced delays while maintaining implementation flexibility through configurable hardware parameters
Data Source
AI summary
In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.


