Single-Channel PWM Decoder Circuit for 5 Ns Signal Periods
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Solution Overview
Problem
Conventional PWM decoder circuits are unable to correctly decode high-frequency PWM signals with periods as short as 5 ns, and existing solutions often require multiple channels, which are either too slow or unreliable against noise, especially in applications like SiC driver circuits and CAN transceivers.
Innovation Solution
A PWM decoder circuit utilizing a single capacitor and current sources or resistors for fast charge/discharge, combined with a comparator or inverter arrangement, allows for decoding high-frequency PWM signals with a single communication channel, achieving accurate and fast decoding of duty cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional PWM decoder circuits are used, then they can decode low-frequency PWM signals, but they are unable to correctly decode high-frequency PWM signals with periods as short as 5 ns
Solution Approach 1:
The patent changes the operational parameters of the decoder circuit by using a single capacitor with fast charge/discharge characteristics and current sources that can operate at high frequencies. The capacitor is charged during the high phase of the PWM signal and discharged during the low phase, with the final voltage level indicating the duty cycle. This parameter-based approach enables accurate decoding of high-frequency PWM signals with periods as short as 5 ns while maintaining reliability.
2Adaptability or versatility
If multiple channels are used to decode high-frequency PWM signals, then decoding coverage is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal single-channel decoder that can handle a wide frequency range from DC to 150 Mbit/s. The circuit uses a single capacitor and current sources that can operate across the entire frequency spectrum, eliminating the need for separate low-frequency and high-frequency decoding channels. This multi-functional approach maintains adaptability while significantly reducing device complexity.
3Speed
If fast charge/discharge circuits are used, then decoding speed is improved, but noise susceptibility increases
Solution Approach 1:
The patent incorporates a comparator that reads the capacitor voltage at the end of each PWM period and uses feedback to control the charging current in the next period. This feedback mechanism ensures that the capacitor reaches a stable voltage level that accurately represents the duty cycle, even in the presence of noise. The comparator's hysteresis further enhances noise immunity by providing a clear threshold for digital output determination.
4Device complexity
If a single channel is used, then device complexity is reduced, but frequency response range is limited
Solution Approach 1:
The patent creates a dynamic single-channel decoder where the capacitor charge/discharge process adapts to the input signal frequency. The circuit automatically adjusts its operation: at low frequencies, the capacitor has sufficient time to charge and discharge fully; at high frequencies up to 150 Mbit/s, the fast current sources and low-capacitance design ensure the capacitor can still reach stable voltage levels within each period. This dynamic behavior enables a wide frequency response range while maintaining simple single-channel architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables decoding of PWM signals with cycles as short as 5 ns, providing a single channel with a wide frequency response from DC to 150 Mbit/s, suitable for SiC driver circuits and CAN transceivers, while being robust against noise and cost-effective.
Implementation Method 1
A PWM decoder circuit may comprise a capacitance C (e.g., a capacitor) having a first terminal coupled to an intermediate node of the circuit
Implementation Method 2
The current generating circuitry may be coupled to an intermediate node of the circuit to charge or discharge the capacitance C as a function of a value of the input signal PWM
Implementation Method 3
A comparator circuit 24 may be coupled between the intermediate node and an output node of the circuit to generate the output signal DATA as a function of a comparison between a voltage signal at the intermediate node and a reference voltage
Data Source
Figure 1A~2A
Figure 2B
Figure 2C
AI summary
A circuit (20A) for decoding a pulse width modulated signal (PWM) comprises an input node (200) configured to receive the pulse width modulated signal (PWM), and an output node (202) configured to provide an output signal (DATA) switching between a first output value and a second output value as a function of the duty-cycle of the input pulse width modulated signal (PWM). A current generating circuitry (22) is coupled between a supply voltage node (Vdd) and a ground voltage node (GND) . The current generating circuitry is coupled to the input node (200) to receive the input pulse width modulated signal (PWM) and is coupled to an intermediate node (204) of the circuit to inject a current (IH) therein or to sink a current (IL) therefrom as a function of the value of the input pulse width modulated signal (PWM). A capacitance (C) has a first terminal coupled to the intermediate node (204), and it is alternatively charged and discharged by the currents (IH, IL) generated by the current generating circuitry (22). A comparator circuit (24) is coupled between the intermediate node (204) and the output node (202). The comparator circuit (24) is configured to sense a voltage signal (Vc) at the intermediate node (204), compare the sensed voltage signal (Vc) to a reference voltage signal (Vref), and drive the output node (202) to the first output value or to the second output value as a function of the comparison, thereby generating the output signal (DATA).