PWM Decoder Circuit for 5 Ns High-Frequency Signal Decoding
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Solution Overview
Problem
Conventional PWM decoder circuits are unable to correctly decode high-frequency PWM signals with periods as short as 5 ns, which is essential for applications like CAN XL bus and silicon carbide (SiC) driver circuits, due to limitations in frequency response and reliability against noise, particularly requiring a single communication channel with wide frequency range.
Innovation Solution
A 'two-cycle' PWM decoder circuit design that includes an input node for receiving PWM signals, current generating circuitry to charge and discharge a capacitor, and a comparator to sense the voltage and generate an output signal based on the duty-cycle, allowing for decoding of high-frequency signals with a single communication channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional PWM decoder circuits are used, then the circuit structure is simple, but the frequency response is limited and cannot decode high-frequency PWM signals with periods as short as 5 ns
Solution Approach 1:
The PWM decoding function is segmented into two separate communication channels: a first channel for low-frequency PWM signals and a second channel for high-frequency PWM signals. Each channel is optimized for its specific frequency range, allowing the system to achieve high frequency response (up to 150 Mbit/s) while maintaining manageable circuit complexity through specialized design for each segment
Solution Approach 2:
The dual-channel PWM decoder is designed to universally handle both low-frequency and high-frequency PWM signals through a single integrated circuit. The circuit incorporates multiple decoders that can process different frequency ranges, enabling one system to perform multiple frequency decoding functions that would otherwise require separate dedicated circuits
2Device complexity
If a single communication channel is used to handle wide frequency range, then the device complexity is reduced, but the reliability against noise deteriorates
Solution Approach 1:
The communication system is segmented into two independent channels, each optimized for specific frequency ranges. This segmentation allows each channel to implement targeted noise filtering and decoding strategies appropriate for its frequency band, improving overall reliability without requiring a single overly complex universal channel
Solution Approach 2:
The patent introduces an intermediary frequency conversion stage that converts high-frequency PWM signals to lower frequencies before decoding. This intermediary approach allows high-frequency signals to be processed with the reliability of low-frequency decoding techniques while maintaining the benefits of high-speed communication
3Speed
If high-frequency PWM decoding is implemented, then the communication speed is improved, but the difficulty of detecting and measuring increases
Solution Approach 1:
An intermediary frequency conversion mechanism is introduced that transforms high-frequency PWM signals into lower frequency signals suitable for standard decoding circuits. This mediator stage simplifies the detection and measurement processes by converting difficult-to-detect high-frequency signals into easily measurable low-frequency signals while preserving the encoded information
Solution Approach 2:
The patent replaces direct high-frequency signal detection mechanisms with indirect detection methods using frequency conversion. Instead of using complex high-speed sampling and detection electronics, the system substitutes a frequency translation approach that uses simpler, more reliable detection circuits operating at converted lower frequencies
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables accurate decoding of PWM signals with cycles as short as 5 ns, improving the frequency response and reliability, and can handle signals from DC to 150 Mbit/s, suitable for applications like SiC driver circuits and CAN XL bus, with reduced complexity and cost compared to existing dual-channel solutions.
Implementation Method 1
a capacitance having a first terminal coupled to the intermediate node, the capacitance being alternatively charged and discharged by the currents generated by the current generating circuitry
Implementation Method 2
a comparator circuit coupled between the intermediate node and the output node; the comparator circuit being configured to sense a voltage signal at the intermediate node, compare the sensed voltage signal to a reference (e.g., threshold) voltage signal
Data Source
AI summary
A circuit for decoding a pulse width modulated (PWM) signal generates an output signal switching between a first and second logic values as a function of a duty-cycle of the PWM signal. Current generating circuitry receives the PWM signal and injects a current to and sinks a current from an intermediate node as a function of the values of the PWM signal. A capacitor coupled to the intermediate node is alternatively charged and discharged by the injected and sunk currents, respectively, to generate a voltage. A comparator circuit coupled to the intermediate node compares the generated voltage to a comparison voltage and drives the logic values of the output signal as a function of the comparison.