PWM Signal Generator Delay Correction Circuit
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Solution Overview
Problem
Existing PWM signal generators face issues with varying delay times due to PVT variations, leading to undesired resolution in switching cycle and duty control, and the addition of DLL circuits increases circuit scale and design costs.
Innovation Solution
A PWM signal generator with a delay circuit unit, selector, PWM signal output unit, delay-amount detector, and digital value generator, which uses a series of delay elements and hardware correction circuits to maintain desired resolution without increasing circuit scale or design costs, by detecting and correcting delay amounts and generating digital values to control switching elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a DLL circuit is added to control delay time, then the resolution of switching cycle and duty can be maintained, but the circuit scale increases and design costs increase
Solution Approach 1:
The patent changes the parameter control approach from using a complex DLL circuit to using a simple counter that counts clock cycles. The delay time is controlled by changing the count value parameter, which directly sets the delay period without requiring additional phase-locked loop components. This parameter-based control maintains resolution while reducing circuit complexity.
Solution Approach 2:
The patent replaces the mechanical/analog DLL circuit system with a digital counting system. Instead of using voltage-controlled oscillators and phase detectors, the invention uses a digital counter that simply counts clock signals to generate the desired delay period. This substitution eliminates the need for complex analog components while maintaining precise delay control.
2Measurement precision
If a DLL circuit is added to control delay time, then the resolution of switching cycle and duty can be maintained, but design costs increase
Solution Approach 1:
The patent uses a simple counter circuit that can be easily implemented in standard CMOS technology, replacing the expensive and complex DLL circuit. The counter requires minimal components and can be synthesized using standard design libraries, significantly reducing both design and manufacturing costs while maintaining the required resolution for switching cycle and duty control.
Solution Approach 2:
The patent replaces the expensive analog DLL circuit with a digital counting system that is easier to design and manufacture. The digital counter can be implemented using standard logic cells or simple state machines, reducing design complexity and manufacturing costs compared to the precision analog components required for DLL circuits.
3Productivity
If delay times of differential buffers are used, then PWM signal can be generated, but the delay times vary due to PVT variations causing undesired resolution
Solution Approach 1:
The patent introduces a feedback mechanism where the counter counts clock cycles and compares the count value against a target delay period. This feedback approach ensures that the actual delay time matches the desired delay, compensating for any PVT variations in the circuit. The counter automatically adjusts to maintain the correct delay period regardless of process, voltage, or temperature changes.
Solution Approach 2:
The patent replaces the analog delay buffer system with a digital counting system that is inherently more stable against PVT variations. The digital counter's operation based on clock cycle counting makes it insensitive to the analog parameter variations that affect differential buffers, thereby maintaining consistent resolution across different operating conditions.
Data Source
AI summary
A PWM signal generator includes a delay circuit unit, which includes a plurality of delay elements connected in series, an output terminal of the delay element in a final stage among the plurality of delay elements and an input terminal of the delay element in an initial stage among the plurality of delay elements being connected to each other; a selector, which selects any one of output signals of the plurality of delay elements based on a digital value; a PWM signal output unit, which outputs a PWM signal based on the output signal selected by the selector; a delay-amount detector, which detects an amount of delay of a signal due to the delay circuit unit; and a digital value generator, which generates the digital value by correcting predetermined data based on the amount of delay detected by the delay-amount detector.