PWM Difference ADC Using Reset Counters for Precise Conversion
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Solution Overview
Problem
Current analog to digital converters face challenges in achieving high accuracy and efficiency, particularly in calibrating timing and handling multiple input signals, which complicates the conversion process.
Innovation Solution
The proposed solution involves a multi-phase clock unit generating phase-shifted clock signals, paired with samplers and PWM modulators, and a processing unit that calculates differences between input signals using counters and sampling latches, eliminating the need for complex timing calibration by resetting counters between sampling iterations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex timing calibration is used to achieve high accuracy in analog to digital conversion, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by resetting counters to a known state before each sampling iteration. This pre-initialization eliminates the need for complex timing calibration between iterations, as each counter starts from a defined baseline state, thereby maintaining measurement precision while reducing device complexity.
Solution Approach 2:
The patent changes the operational parameter of the counters by resetting them between sampling iterations. This parameter change (from continuous counting to periodic reset) allows the system to maintain accurate timing measurements without requiring complex calibration circuits, thus improving the ratio of measurement precision to device complexity.
2Productivity
If multiple counters are used to handle multiple input signals simultaneously, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the signal processing task into multiple parallel counter units, each handling a specific phase-shifted clock signal. This segmentation allows simultaneous processing of multiple input signals (improving productivity) while keeping each counter's logic simple and standardized (controlling device complexity through modular repetition).
Solution Approach 2:
The patent implements universality by designing identical counter structures that can be replicated N times to handle N different phase-shifted clock signals. Each counter performs the same function (timing measurement) but operates on different signals, enabling multi-signal processing without proportionally increasing overall system complexity.
3Measurement precision
If phase-shifted clock signals are used for sampling multiple signals, then measurement precision is improved, but ease of operation worsens
Solution Approach 1:
The patent applies self-service by having the multi-phase clock unit automatically generate phase-shifted clock signals with fixed, predetermined phase relationships. This self-generating approach eliminates the need for manual synchronization adjustments, allowing the system to maintain high timing resolution while improving ease of operation through automatic phase management.
Solution Approach 2:
The patent uses periodic action by generating clock signals with fixed phase shifts (e.g., 90 degrees apart) that repeat consistently across sampling iterations. This periodic, predictable timing pattern simplifies the operation and synchronization of multiple counters, as the phase relationships are established once and maintained automatically throughout operation.
Data Source
AI summary
An ADC that includes a processing unit configured to receive from first sampling latches N first PWM pulse start counter values and N first PWM pulse end counter value, receive from second sampling latches, N second PWM pulse start counter values and N second PWM pulse end counter value; (c) select a counter that is coupled to a selected sampling latch; (d) calculate an estimated difference between first and second input analog signals based on at least readings of the selected latch. The readings of the selected counter include a first PWM pulse start counter value latched by the selected latch, a first PWM pulse end counter value latched by the selected latch, a second PWM pulse start counter value latched by the selected latch, and a second PWM pulse end counter value latched by the selected latch; and (e) output a digital output signal indicative of the estimated difference.