PWM Gate Drive Dithering to Reduce Power Converter EMI

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Solution Overview

Problem

Power converters using pulse width modulated (PWM) signals often introduce electromagnetic interference (EMI) due to switching, which can adversely affect nearby receiver circuitry.

Innovation Solution

A circuit device incorporating a programmable counter system that introduces dither into the PWM signal by varying the reset threshold of a counter, spreading energy away from selected frequencies and reducing EMI through controlled noise in the output power spectrum.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If PWM switching is used to control power conversion, then power conversion efficiency is improved, but electromagnetic interference is generated that adversely impacts nearby receiver circuitry

Engineering Contradiction:
Improvepower conversion efficiencyVSAvoidelectromagnetic interference
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent applies periodic action by introducing dither signals that periodically vary the PWM switching timing. This creates intentional, controlled periodic variations in the switching pattern that spread the spectral energy of the PWM signal across multiple frequencies, thereby reducing peak EMI at any single frequency while maintaining the overall switching function for power conversion efficiency

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent implements parameter changes by dynamically adjusting the switching timing parameters of the PWM signal through dither injection. The dither signal modifies the duty cycle and switching instant parameters in a controlled manner, transforming the fixed-frequency PWM signal into a frequency-modulated signal that achieves EMI reduction while preserving power conversion performance

Inventive Principle:
Principle #35Parameter changes

2Object-generated harmful factors

If dither is introduced to reduce peak energy at specific frequencies, then electromagnetic interference is minimized, but the complexity of the PWM circuit increases

Engineering Contradiction:
Improveelectromagnetic interferenceVSAvoidPWM circuit complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent applies the nested doll principle by integrating the dither generation and injection functions within the existing PWM controller structure. The dither signal is generated using resources already present in the PWM circuit (such as existing counters and timing generators), nesting the EMI reduction functionality within the power conversion control architecture rather than adding completely separate circuitry

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent implements self-service by designing the dither injection mechanism to utilize the PWM circuit's own internal resources for generating and applying the dither signal. The existing timing and control infrastructure of the PWM circuit is repurposed to create the dither effect, allowing the circuit to serve both its primary power conversion function and the secondary EMI reduction function without requiring extensive external additions

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS7800415B2Circuit device to produce an output signal including dither
Publication Date: 2010.09.21 SILICON LABORATORIES INC
  • US7800415B2 patent drawing
  • US7800415B2 patent drawing
  • US7800415B2 patent drawing

AI summary

In a particular embodiment, a circuit device includes a count zero circuit having a first counter to receive a clock signal and to produce a count zero signal based on the clock signal and having a second counter to generate a reset control signal to control a reset of the count zero circuit. The circuit device further includes a turnoff circuit to receive the clock signal and to produce a turn off signal based on the clock signal. Further, the circuit device includes a pulse width modulated (PWM) latch circuit adapted to produce a gate drive signal based on the count zero signal and the turn off signal, where timing of an edge of the gate drive signal varies based on the reset control signal.