PWM Frequency Control Using Dithering and Variable Delay
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Solution Overview
Problem
Existing digital PWM systems face challenges in achieving high frequency resolution due to the impracticality of using high-frequency clocks, which are power-intensive and costly, and often result in undesirable behaviors like limit cycling and signal distortion.
Innovation Solution
The implementation of a combination of frequency dithering and a variable delay circuit allows for improved PWM frequency resolution using realizable circuit components and clock operating frequencies, enabling finer frequency control without the need for infinite delay circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-frequency clocks are used to improve PWM frequency resolution, then frequency resolution is improved, but power consumption increases and cost becomes prohibitive
Solution Approach 1:
The patent segments the frequency control into two independent components: a digital PWM counter that sets the base frequency period, and an analog delay circuit that provides fine frequency adjustment. This segmentation allows the system to achieve high frequency resolution without requiring a high-frequency clock, thereby reducing power consumption while maintaining measurement precision.
Solution Approach 2:
The patent introduces an analog delay circuit as an intermediary between the digital PWM counter and the final PWM output. This intermediary component translates digital period values into precise time delays, enabling fine frequency resolution without directly increasing clock frequency, thus avoiding the associated power consumption penalties.
2Measurement precision
If high-frequency clocks are used to improve PWM frequency resolution, then frequency resolution is improved, but device cost becomes prohibitive
Solution Approach 1:
The patent divides the frequency control function into separate digital and analog stages, allowing each to be optimized independently. The digital PWM counter uses standard clock frequencies, while the analog delay circuit provides the necessary fine resolution. This approach reduces device cost by avoiding the need for expensive high-frequency clock generators and associated high-speed digital circuitry.
Solution Approach 2:
The analog delay circuit serves as a cost-effective intermediary that bridges the gap between standard digital PWM counters and high-resolution frequency control requirements. By using readily available analog delay components rather than expensive high-frequency digital logic, the overall device cost is reduced while maintaining manufacturing simplicity.
3Measurement precision
If frequency dithering is used in resonant mode power conversion circuits, then PWM frequency resolution is improved, but ripple currents and voltages are generated
Solution Approach 1:
The patent implements dynamic frequency adjustment by continuously varying the delay circuit control voltage based on the desired PWM frequency. This dynamic approach allows the system to achieve fine frequency resolution without using frequency dithering, thereby avoiding the generation of ripple currents and voltages while maintaining the ability to precisely control PWM frequency in resonant mode circuits.
Solution Approach 2:
The patent replaces the digital frequency dithering mechanism with an analog delay circuit that provides continuous frequency adjustment. This substitution eliminates the discontinuous frequency switching that causes ripple effects, while still achieving the desired high frequency resolution through smooth analog control of the delay element.
Data Source
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AI summary
Using a combination of frequency dithering of a PWM counter and a variable time delay circuit yields improved PWM frequency resolution with realizable circuit components and clock operating frequencies. A controllable time delay circuit lengthens a PWM signal during the first PWM cycle. During the second PWM cycle, the PWM period is increased beyond the desired amount, but the delay is reduced during this second PWM cycle to achieve the correct (desired) PWM signal period. The dithering of the PWM signal period enables the time delay circuit to be "reset" so that an infinite delay circuit is not required. The time delay circuit provides short term (one cycle) frequency adjustment so that the resulting PWM cycle is not dithered and has a period at the desired frequency resolution.