Multi-Stage Driver Circuit for PWM Slew Rate and EME Control
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Solution Overview
Problem
Existing driver circuits for resistor-inductor (RL) loads face challenges in managing high PWM actuation frequencies, leading to increased dead time and electromagnetic emission (EME), which can limit system performance and violate electromagnetic compatibility standards like IEC 61967-4.
Innovation Solution
The driver circuit employs a high-side and low-side power switch configuration with combinational logic and comparators to control the power switches' operation, using multiple pull-up currents with different values during the turn-on phase of the low-side power switch to minimize dead time and regulate current and voltage slew rates, thereby reducing EME.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high PWM actuation frequencies are used, then productivity is improved, but dead time increases and electromagnetic emission increases
Solution Approach 1:
The driver circuit dynamically adjusts the gate drive current in multiple stages during the power switch transition. A first higher current is applied initially to quickly charge the gate capacitance, then a second lower current is applied to complete the transition, optimizing both switching speed and EME reduction across different operating conditions
Solution Approach 2:
The circuit changes the gate drive current parameter during the switching transition by using different current values for different phases of the transition. This parameter change allows the circuit to achieve fast switching when needed while reducing EME during other phases, effectively managing the dead time at high PWM frequencies
2Productivity
If high PWM actuation frequencies are used, then productivity is improved, but electromagnetic emission increases
Solution Approach 1:
The driver circuit dynamically adjusts the gate drive current in multiple stages during the power switch transition. A first higher current is applied initially to quickly charge the gate capacitance, then a second lower current is applied to complete the transition, optimizing both switching speed and EME reduction across different operating conditions
Solution Approach 2:
The circuit employs periodic multi-stage current pulsing to the gate terminal, where different current levels are applied in sequence during each switching cycle. This periodic action with varying current amplitudes allows the system to maintain high PWM frequencies while reducing peak EME emissions through controlled current profiles
3Manufacturing precision
If multiple pull-up currents with different values are used, then current and voltage slew rates are controlled, but device complexity increases
Solution Approach 1:
The gate drive current is segmented into multiple discrete current levels applied at different stages of the switching transition. By dividing the single current source into multiple current stages, the circuit achieves precise slew rate control without requiring a completely complex current regulation system
Solution Approach 2:
The circuit prepares multiple current levels in advance and selects the appropriate current stage based on the switching phase. This preliminary preparation of current options allows precise control of voltage and current slew rates during the transition without adding significant complexity to the overall driver architecture
Data Source
AI summary
An integrated circuit (IC) includes: an input terminal; an output terminal; a first reference voltage terminal and a second reference voltage terminal; a high-side power switch coupled between the first reference voltage terminal and the output terminal; a low-side power switch coupled between the output terminal and the second reference voltage terminal; a first combinational logic and a second combination logic that are coupled to the input terminal; a first driver coupled between the first combinational logic and the high-side power switch; a second driver coupled between the second combinational logic and the low-side power switch; and first comparators coupled to the second combinational logic, where the first comparators are configured to compare a voltage difference between load path terminals of the high-side power switch with a first threshold and a second threshold.