PWM Driver Signal Overlay for Error Detection
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Solution Overview
Problem
Existing methods for operating PWM outputs of drivers for power semiconductors do not effectively prioritize the timely detection of error signals over analog value transmission, potentially leading to information loss or delayed signal changes, especially in time-critical applications.
Innovation Solution
The method involves overlaying the PWM signal with a high-frequency additional signal when an error condition is detected, ensuring the error signal is transmitted with a frequency significantly higher than the PWM frequency, allowing for timely detection while minimizing disruption to the analog value transmission by selecting signal levels that retain the original PWM signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the PWM signal is used to transmit both analog values and binary error signals separately, then the transmission path is simple, but the error signal detection is delayed and analog value information may be lost
Solution Approach 1:
The patent combines the transmission of analog values and binary error signals into a single PWM transmission path. The error signal is encoded by modulating the PWM signal's duty cycle: when an error occurs, the PWM signal maintains a high level for the entire period, while normally the high level duration corresponds to the analog value. This merging eliminates the need for separate transmission paths while enabling timely error detection through duty cycle analysis.
Solution Approach 2:
The patent changes the duty cycle parameter of the PWM signal to encode error information. Under normal conditions, the duty cycle represents the analog value. When an error occurs, the duty cycle is changed to 100% (high level for the entire period), creating a distinct parameter state that allows immediate error detection without affecting the transmission path structure.
2Loss of time
If a high-frequency additional signal is overlaid on the PWM signal for error transmission, then error detection timing is improved, but signal integrity may be compromised
Solution Approach 1:
The patent uses periodic PWM signals with controlled duty cycles to transmit both analog values and error signals. By making the error indication a periodic feature (100% duty cycle during error periods), the system achieves timely error detection while maintaining signal integrity through the regular, predictable nature of the PWM waveform that receivers can reliably interpret.
Solution Approach 2:
The error signal is encoded into the PWM signal structure itself before transmission, rather than adding a separate high-frequency signal that might interfere. The duty cycle is preliminarily set to indicate error status, ensuring that error information is embedded in a way that preserves overall signal integrity and can be extracted without disrupting the analog value transmission.
3Productivity
If the PWM signal duty cycle is used to represent analog values, then transmission efficiency is high, but error signal priority transmission is difficult
Solution Approach 1:
The patent uses parameter changes in the duty cycle to achieve both efficient analog value transmission and reliable error signal priority. The duty cycle parameter serves dual purposes: its normal variation encodes analog values for efficient transmission, while its extreme state (100% duty cycle) encodes error signals with high priority. This parameter duality allows the system to maintain transmission efficiency while ensuring error signals are reliably detected and prioritized.
Data Source
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AI summary
In a method for outputting an analog value (A) at a PWM output (4) of a driver (2) for a power semiconductor,: - the analog value (A) is converted into a PWM signal (6) with two signal levels (Hi,Lo) and a fixed PWM frequency (fP), and - when a binary auxiliary value (F) is inactive (0): - the PWM signal (6) is output at the PWM output (4), or - when the auxiliary value (F) is active (1): - the PWM signal (6) is output at the PWM output (4) together with an auxiliary signal (18), wherein the current signal level (Hi,Lo) of the PWM signal (6) and the other signal level (Lo,Hi) are output alternately as the auxiliary signal (18) with a signal frequency (fs) greater than the PWM frequency (fP).