PWM Error Calibration Circuit for Wide-Range Duty Precision
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Solution Overview
Problem
Existing PWM-based internal control circuits for LED lamps suffer from low precision in PWM signal generation, requiring large capacitors that occupy space and increase costs, and experience significant errors due to small current variations, while also having unstable duty ratios and high jitter in the average current.
Innovation Solution
A PWM signal generation and error calibration circuit utilizing an amplifier, comparators, PMOS field-effect transistors, variable resistors, and a 14-bit counter to generate triangle-wave voltage with variable current, reducing the need for large capacitors and improving precision by calibrating duty ratios at two voltage points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of stationary object
If a small current (1uA) is used to charge the capacitor in PWM signal generation, then the capacitor size can be reduced, but the error among chips becomes significantly larger
Solution Approach 1:
The patent changes the current parameter from a fixed small value (1uA) to a larger value (100uA) to reduce chip error variation while still achieving compact capacitor size through the improved current-driven PWM generation circuitry
2Speed
If a low PWM frequency is set, then a relatively large capacitor is required, which takes much space and increases cost
Solution Approach 1:
The patent employs a 14-bit counter instead of traditional capacitor-based timing, fundamentally changing the frequency determination parameter from capacitor size to counter clock divisions, enabling low PWM frequencies without large capacitors
Solution Approach 2:
The patent replaces the mechanical/electrical capacitor charging system with a digital counting system, where frequency is determined by clock signal divisions rather than RC time constants, eliminating the direct relationship between low frequency and large capacitor size
3Device complexity
If an 8-bit ADC is used to convert voltage to digital signal for PWM generation, then the circuit complexity is reduced, but the duty ratio precision is limited with theoretical maximum error of 1/256
Solution Approach 1:
The patent changes the resolution parameter from 8-bit to 10-bit ADC conversion, improving duty ratio precision from 1/256 to 1/1024 while maintaining reasonable circuit complexity through efficient conversion architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for a smaller capacitor size, reduced chip costs, broader frequency range, and precise PWM signal generation with improved linearity of duty ratios, addressing the issues of space, cost, and precision in existing PWM-based internal control circuits.
Implementation Method 1
an amplifier OP1, an amplifier OP2, a comparator CMP1, a comparator CMP2
Implementation Method 2
a comparator CMP1, a comparator CMP2
Implementation Method 3
PMOS field-effect transistors M1-M16
Implementation Method 4
a capacitor C1
Implementation Method 5
a 14-bit counter
Data Source
AI summary
A PWM signal generation and error calibration circuit includes an amplifier OP1, an amplifier OP2, a comparator CMP1, a comparator CMP2, PMOS field-effect transistors M1-M16, a resistor R14, a resistor R_FRE, variable resistors R15-R16, a resistor R17, a capacitor C1, a matched resistance module circuit, a current drain IDC, and a 14-bit counter. The PWM signal generation and error calibration circuit saves chip costs and supports a wide PWM signal frequency range, while being able to calibrate all duty cycle errors of PWM signals in the range between 0% and 100% with improved accuracy.