PWM Feedback Clock Circuit for Faster PLL Locking
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Solution Overview
Problem
Existing phase lock circuits (PLLs) require external devices such as counter control circuits, loop filters, dual modulus prescalers, and voltage controlled oscillators (VCOs), which increase cost and complexity, and also take many cycles to lock onto the desired phase/frequency when stepping from one frequency to another.
Innovation Solution
A Core Independent Peripheral (CIP) PLL device is designed to require limited external devices and reduces the number of cycles needed to lock onto the desired phase/frequency by incorporating a reference divider circuit, phase-frequency detector circuit, loop filter circuit, voltage controlled oscillator circuit, divider circuit, and pulse-width modulation (PWM) circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external devices (counter control circuits, loop filters, dual modulus prescalers, VCOs) are used in PLL, then the PLL can generate phase-coherent clock sources, but the cost and complexity of the solution increase
Solution Approach 1:
The patent integrates the PLL functionality directly into the CPU core, merging previously separate external devices (counter control circuits, loop filters, dual modulus prescalers, VCOs) into a unified internal structure. This consolidation eliminates the need for multiple external components while maintaining phase-coherent clock source generation capability.
Solution Approach 2:
The CPU core is designed to perform multiple functions: it acts as both the processing unit and the PLL controller. The core independently manages clock generation, phase detection, and frequency synthesis without requiring dedicated external peripheral devices, thereby reducing overall system complexity while maintaining reliability.
2Ease of operation
If external devices are used for PLL control, then the PLL can be controlled via external control bus (SPI or I2C), but the cost and complexity increase
Solution Approach 1:
The patent extracts the control functionality from external devices and relocates it directly into the CPU core. By removing the dependency on external control buses (SPI or I2C) and external control devices, the system simplifies the control architecture while maintaining full PLL control capability through internal core mechanisms.
3Reliability
If traditional PLL is used, then it can generate clock sources, but it takes many cycles to lock onto the desired phase/frequency when stepping from one frequency to another
Solution Approach 1:
The patent implements frequency prediction and pre-adjustment mechanisms within the CPU core. Before a frequency step occurs, the core anticipates the required phase and frequency adjustments, preparing the necessary control signals in advance. This preliminary action significantly reduces the number of cycles needed to lock onto the new frequency, as the system is already partially configured for the target state.
Solution Approach 2:
The patent employs dynamic frequency adjustment mechanisms that adapt the PLL locking process based on the specific frequency transition requirements. The core dynamically modifies control parameters during frequency stepping, optimizing the locking speed for each transition scenario rather than using a fixed, conservative locking approach.
Data Source
AI summary
A device may have a reference divider circuit to divide a reference clock, a phase-frequency detector circuit to detect a detected phase difference and a detected frequency difference based on the reference divider output and a feedback clock, a loop filter circuit to filter the detector output, a voltage controlled oscillator (VCO) control output pin coupled to the loop filter output, a VCO clock divider control output pin to select a divisor of an external clock divider circuit, a divided VCO clock input pin for coupling to an output of the external clock divider circuit, a pulse-width modulation (PWM) circuit having a PWM clock input coupled to the divided VCO clock input pin, a period register to store a period value, a duty cycle register to store a duty cycle value and a pulse-width modulated output based on the period value and the duty cycle value.