PWM Filtering Circuit Using D Flip-Flop Pulse Width Gating
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Solution Overview
Problem
Existing filtering circuits for pulse width modulated (PWM) signals struggle to reliably remove pulses with duty cycles outside a predetermined range without introducing distortion, which can degrade system performance in applications like high-frequency class-D amplifiers.
Innovation Solution
A digital filtering circuit utilizing a D flip-flop and specific logic circuits with delay lines, inverters, AND/NAND gates, and OR gates to generate clock and reset signals, ensuring pulses within a predetermined range are filtered while maintaining the original pulse width without distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a simple RC filter is used to remove pulses with duty cycles outside the predetermined range, then the filtering function is achieved, but the pulse shape is distorted and system performance degrades
Solution Approach 1:
The filtering function is segmented into multiple independent digital logic components: delay lines for time measurement, comparators for duty cycle evaluation, and control logic for pulse generation. Each component performs a specific function, allowing precise control over the filtering process without introducing distortion to the output pulses.
Solution Approach 2:
The continuous analog RC filtering mechanism is replaced with a discrete digital logic system. Instead of using continuous time constants and analog component values, the invention uses digital delay elements, logic gates, and state machines to achieve pulse width measurement and filtering decisions, eliminating the inherent distortion of analog RC circuits.
2Reliability
If pulses with duty cycles outside the predetermined range are removed, then the system reliability is improved, but the circuit complexity increases
Solution Approach 1:
The circuit uses periodic clock signals to drive the delay lines and control logic, enabling systematic measurement of pulse widths through discrete time steps. This periodic operation allows complex filtering logic to be implemented in a structured, repeatable manner that manages complexity through regularity.
Solution Approach 2:
Delay lines serve as intermediary elements between the input PWM signal and the filtering decision logic. These delay lines temporarily store and shift the signal through defined time periods, providing a mechanical means to measure pulse width without requiring complex real-time analysis, thus simplifying the overall circuit architecture.
Data Source
AI summary
A filtering circuit for filtering a pulse width modulated (PWM) signal includes a D flip-flop having an input terminal configured to be coupled to a logic high signal and having an output terminal coupled to an output terminal of the filtering circuit; and a circuit coupled between an input terminal of the filtering circuit and the D flip-flop, the circuit configured to, for a first pulse of the PWM signal having a duty cycle within a pre-determined range: generate a positive pulse at a clock terminal of the D flip-flop as a clock signal of the D flip-flop; and generate a negative pulse at a reset terminal of the D flip-flop as a reset signal of the D flip-flop, wherein a duration between a rising edge of the positive pulse and a falling edge of the negative pulse is equal to a duration of the first pulse of the PWM signal.