PWM Signal Frequency Adjustment for Buck Regulator Duty Cycle
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional voltage-buck switched-mode power supplies face limitations in duty cycle due to intrinsic latency in control circuits, leading to restricted working range and high complexity or power consumption when attempting to increase duty cycle.
Innovation Solution
A method that compares the input voltage with a threshold voltage and decreases the frequency of the pulse-width modulation signal, allowing the duty cycle to be adjusted by increasing the period of the signal, thereby enhancing the performance of the voltage regulator without increasing complexity or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the duty cycle is increased to improve low-dropout performance, then the regulator can maintain functionality at low input-output voltage differences, but the intrinsic latency of the control circuit prevents the duty cycle from reaching 100%
Solution Approach 1:
The patent applies preliminary action by anticipating the latency-induced duty cycle limitation and compensating for it in advance. The method pre-calculates the effective duty cycle considering the control circuit's intrinsic latency, and adjusts the PWM signal generation accordingly to achieve the desired effective duty cycle despite the latency delay.
Solution Approach 2:
The patent changes the parameter of duty cycle calculation by introducing a compensation mechanism that accounts for control circuit latency. Instead of using the raw PWM duty cycle, the system calculates an compensated duty cycle that factors in the latency delay, thereby achieving accurate low-dropout regulation even when the nominal duty cycle cannot reach 100%.
2Productivity
If conventional solutions are used to increase the duty cycle, then the performance improves, but the complexity and silicon area substantially increase
Solution Approach 1:
The patent applies self-service by making the control circuit compensate for its own latency automatically. The system uses its internal resources to calculate and apply the latency compensation without requiring external intervention or additional complex circuitry, thereby improving duty cycle performance while maintaining simplicity.
Solution Approach 2:
The patent achieves performance improvement through parameter changes in the duty cycle calculation algorithm rather than through hardware complexity increases. By modifying how the duty cycle is computed and applied, the system achieves better low-dropout performance using the existing control circuit infrastructure.
3Productivity
If the control circuit latency is decreased to increase the duty cycle, then the performance improves, but the power consumption and silicon area substantially increase
Solution Approach 1:
The patent achieves duty cycle improvement through parameter changes in the control algorithm rather than through hardware modifications. By adjusting the duty cycle calculation to compensate for latency, the system achieves better performance without increasing power consumption or silicon area.
Data Source
AI summary
A method for increasing performance of a voltage-buck switched-mode voltage regulator includes generating a first pulse-width modulation signal based on a clock signal, decreasing a frequency of the clock signal to form a modified clock signal, passing the modified clock signal to a digital modulation circuit as a regulated clock signal; and generating a second pulse-width modulation signal based on the regulated clock signal using the digital modulation circuit. The first pulse-width modulation signal includes a period T1 and an off duration D2 corresponding to a first duty cycle. The off duration D2 is an intrinsic pulse-width modulation signal generation latency. The second pulse-width modulation signal includes a period T2 and the off duration D2. The decreased frequency of the modified clock signal causes T2 to be greater than T1 such that a second duty cycle of the second pulse-width modulation signal is increased relative to the first duty cycle.