Single-Die PWM Gate Driver Isolation for Noise Coupling Control

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Solution Overview

Problem

Noise coupling between noise generating and noise sensitive circuits in a system-on-a-chip integration leads to poor performance in noise sensitive circuits due to voltage and current induced noise couplings, which are difficult to eliminate without increasing pin counts or compromising signal integrity.

Innovation Solution

An integrated noise isolation circuit with a floating structure and high voltage level shifters is implemented on a single silicon substrate, isolating noise sensitive circuits from noise generating circuits by terminating noise currents and avoiding capacitive coupling, allowing for noise immune signal transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If noise sensitive circuits and noise generating circuits are integrated on a single silicon die, then device integration and productivity are improved, but noise coupling between circuits increases causing performance degradation

Engineering Contradiction:
Improvedevice integrationVSAvoidnoise coupling
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent divides the silicon die into multiple isolated substrates, each containing either noise-sensitive circuits or noise-generating circuits. This physical segmentation prevents noise coupling while maintaining integration benefits, as each substrate operates independently with its own signal processing path.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary substrate that receives signals from noise-sensitive circuits and transmits them to noise-generating circuits. This intermediate layer acts as a buffer, isolating the two circuit types while enabling signal transfer, thus preventing direct noise coupling.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If separate power supply lines are used to avoid noise injection, then noise immunity is improved, but device complexity and pin count increase

Engineering Contradiction:
Improvenoise immunityVSAvoidpin count
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

By segmenting the device into separate substrates for noise-sensitive and noise-generating circuits, the patent eliminates the need for separate power supply lines. Each substrate can share common power supplies without causing noise injection, as the physical isolation prevents noise coupling through shared power rails.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If floating well structure is used for high-side driver, then gate drive functionality is improved, but dV/dt induced noise injection to substrate increases

Engineering Contradiction:
Improvegate drive functionalityVSAvoiddV/dt induced noise
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the floating well structure from the main substrate by placing it on a separate substrate. This removes the source of dV/dt induced noise from proximity to noise-sensitive circuits, eliminating the harmful noise injection while preserving the high-side driver functionality on its own isolated substrate.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively minimizes noise coupling, enhancing the performance of noise sensitive circuits with improved common mode noise rejection and accurate dead-time insertion, while maintaining efficient signal routing and reducing the impact of noise on substrate nodes.

Implementation Method 1

Two kinds of noise couplings are present inside the gate driver IC, they are voltage induced capacitive coupling, and current and common stray impedance induced voltage coupling.

Methodology Applied
Scientific EffectCapacitive coupling: Capacitance

Implementation Method 2

An integrated noise isolation circuit is provided on a single silicon substrate die having a structural arrangement that minimizes noise... at least one floating structure for isolating influence of the noise

Methodology Applied
Scientific EffectReverse-biased PN junction isolation: Diode

Data Source

PatentUS7528651B2Noise free implementation of PWM modulator combined with gate driver stage in a single die
Publication Date: 2009.05.05 INFINEON TECHNOLOGIES AMERICAS CORP
  • US7528651B2 patent drawing
  • US7528651B2 patent drawing
  • US7528651B2 patent drawing

AI summary

An integrated noise isolation circuit on a single silicon substrate die having a structural arrangement that minimizes noise. The integrated circuit including a noise sensitive circuit including an input stage; a noise generating circuit including an output stage; at least one high voltage level shift circuit coupling the noise generating and noise sensitive circuits for transferring a signal from the input to the output stage; and at least one floating structure for isolating influence of the noise.