Pulse Width Modulation Circuit Jitter Reduction
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Solution Overview
Problem
Conventional pulse width modulation circuits face challenges in achieving fast and precise operation, particularly at high frequencies like 100 MHz with 8-bit resolution, due to limitations in CMOS technology, and fine-tuning frequency in multiphase clock generation circuits leads to jitter and degraded performance.
Innovation Solution
A pulse width modulation circuit with a multiphase clock generation section that includes a phase-locked loop circuit, a clock selection circuit, and a control circuit for fine-adjusting the frequency of multiphase clock signals, using phase interpolation and a clock selection mechanism to reduce jitter and enhance precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If counter method or delay method is used in conventional pulse width modulation circuits, then circuit implementation is simpler, but operation speed and precision cannot achieve fast and precise operation at 100 MHz with 8-bit resolution
Solution Approach 1:
The invention divides the pulse width modulation operation into multiple parallel segments using an interleaved structure with multiple PWM circuits operating at different phases. This segmentation allows the system to achieve higher effective resolution (e.g., 10-bit or 12-bit) by combining results from multiple lower-resolution circuits (e.g., 8-bit each), thereby improving speed and precision without requiring a single complex high-performance circuit.
Solution Approach 2:
The invention introduces a temporal dimension through phase interpolation and interleaving. Instead of achieving high resolution through a single circuit operating at one frequency, the system uses multiple circuits operating at offset phases and combines their outputs over time. This dimensional approach transforms the problem from a spatial constraint (single circuit performance) to a temporal solution (multi-phase combination).
2Measurement precision
If interleaving processing is performed to relax the 40 ps constraint, then operation precision can be improved, but circuit scale increases and phases of each stage scatter
Solution Approach 1:
The invention merges multiple PWM circuit outputs through a combination circuit that integrates the phase-interleaved signals. By combining the outputs of multiple lower-resolution PWM circuits in a coordinated manner, the system achieves higher effective resolution without requiring each individual circuit to be extremely complex. The merging process consolidates the precision improvements while managing circuit scale.
Solution Approach 2:
The invention implements feedback mechanisms through phase-locked loops (PLL) that synchronize and maintain the phase relationships between multiple PWM circuits. The feedback control ensures that phase interpolation remains accurate and that the combined output achieves the desired precision. This feedback approach maintains precision while preventing phase scattering that would otherwise increase circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables rapid and precise pulse width modulation with the ability to fine-tune frequencies, improving grayscale control in laser beam printers and reducing circuit complexity and cost.
Implementation Method 1
The multiphase clock generation circuit 2 generates multiphase clock signals by phase interpolation of intermediate clock signals generated by a phase-locked loop circuit
Data Source
AI summary
A pulse width modulation circuit comprises a multiphase clock generation section which generates multiphase clock signals based on a reference clock, and a pulse width modulation signal generation section which generates pulse width modulation signals based on input data and on multiphase clock signals generated by the multiphase clock generation section. The multiphase clock generation section has a phase-locked loop circuit and a clock selection circuit which selects an arbitrary clock signal from among the multiphase clock signals and outputs the selected clock signal to the phase-locked loop circuit as a feedback clock.