Pulse Width Modulation System for Finer LED Display Brightness Control
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Solution Overview
Problem
Existing LED display systems have a large step size in adjusting the duration of the high level in each period of the driving current, which limits the fineness of the LED display.
Innovation Solution
A system for pulse width modulation that includes a clock-signal generating circuitry, pulse generating circuitry, phase-locked loop, second voltage-controlled delayer, and logic controller, which allows for a small step size adjustment of the pulse width by delaying the original PWM signal by a preset duration, resulting in a target PWM signal with a pulse width that is the sum of the original and the delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the pulse width is adjusted using conventional PWM methods, then the LED display can be controlled, but the step size of adjustment is large which reduces fineness
Solution Approach 1:
The patent segments the pulse width adjustment into two parts: a coarse adjustment component (original PWM signal with integer multiple of minimum period) and a fine adjustment component (delayed PWM signal with sub-period delay). By superimposing these two components, the system achieves both coarse control and fine adjustment capabilities, resolving the contradiction between control capability and adjustment precision.
Solution Approach 2:
The patent introduces a time dimension to the PWM adjustment by using voltage-controlled delayers to create precise time delays (1/N to N/N of clock period) in addition to the conventional pulse width modulation. This time-domain manipulation enables fine-grained pulse width adjustment beyond the conventional integer multiple limitation, thereby improving display fineness.
2Manufacturing precision
If the minimum operating period of digital circuit is reduced, then the step size can be reduced, but the complexity of the system increases
Solution Approach 1:
The patent introduces voltage-controlled delayers as intermediary components between the clock signal generator and the PWM output. These delayers act as mediators that translate voltage control signals into precise time delays, enabling fine pulse width adjustment without requiring the digital circuit to operate at higher frequencies. This intermediary approach resolves the contradiction by providing fine adjustment capability through analog time-delay mechanisms rather than purely digital high-speed operation.
Solution Approach 2:
The patent changes the control parameter from direct pulse width modulation (which requires high-frequency digital operation) to voltage-controlled time delay (which uses lower-frequency analog control). By manipulating the delay time parameter through voltage control rather than directly controlling pulse width through high-speed digital logic, the system achieves fine adjustment with reduced complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables a finer adjustment of the LED display's brightness, improving the overall fineness and performance of the display by allowing for smaller step sizes in pulse width modulation.
Implementation Method 1
a phase-locked loop, configured to generate a control voltage according to the clock signal
Implementation Method 2
a second voltage-controlled delayer, identical to a first voltage-controlled delayer in the phase-locked loop in structure, where the second voltage-controlled delayer is configured to delay, under excitation of the control voltage that is outputted by a filter in the phase-locked loop, the original PWM signal in phase by preset delay duration to obtain a to-be-superimposed signal
Implementation Method 3
a logic controller, configured to superimpose the to-be-superimposed signal with the original PWM signal to generate a target PWM signal
Data Source
AI summary
A pulse width modulation system. Considering that a phase-locked loop can reduce a pulse width of a clock signal by increasing the frequency, in the present application, by means of a control voltage outputted by a filter in the phase-locked loop, an external second voltage-controlled retarder which has the same structure as a voltage-controlled retarder in the phase-locked loop can shift a phase of an original PWM signal backwards by a preset delay duration (less than one clock signal period) to obtain a signal to be superimposed. In this way, a target PWM signal of which the pulse width is the sum of the pulse width of the original PWM signal and the preset delay duration can be generated by superposing the signal to be superposed and the original PWM signal.