PWM Circuit Minimum Pulse Width Control
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Solution Overview
Problem
Conventional PWM circuits are limited in achieving small pulse widths and duty cycles due to insufficient overdrive, leading to pulse skipping and instability at higher switching frequencies, and require diode circuits for zero percent duty cycle which introduce noise and temperature-dependent issues.
Innovation Solution
A PWM circuit with a comparator and latching circuit that generates a pulse width modulated signal with a rising and falling edge, using a sawtooth ramp signal and a periodic set signal with a 25% pulse width of the switching frequency, allowing for adequate overdrive and zero percent duty cycle without a DC offset, enabling operation at higher frequencies like 4 MHz with small pulse widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the switching frequency is increased to improve performance, then the pulse width decreases, but the PWM comparator cannot produce adequate overdrive below a minimum pulse width
Solution Approach 1:
The patent applies preliminary action by pre-charging the ramp signal to a non-zero voltage level before the comparison cycle begins. This head-start voltage ensures that when the high-frequency switching occurs, the ramp signal already has sufficient voltage differential (overdrive) to drive the comparator, even when the available pulse width is very small. This preliminary voltage preparation resolves the contradiction by enabling reliable PWM signal generation at high frequencies without requiring large minimum pulse widths.
2Manufacturing precision
If the pulse width is reduced to achieve smaller duty cycles, then the power control precision improves, but the comparator overdrive becomes insufficient
Solution Approach 1:
The ramp signal is pre-charged to a non-zero voltage level during a precharge phase before the actual PWM comparison begins. This preliminary action ensures that when the pulse width is reduced for precise power control, the ramp signal already has sufficient voltage headroom to provide adequate comparator overdrive. The precharged voltage level acts as a buffer that maintains comparator drive capability even when the final pulse width is very small, thus resolving the contradiction between precision and overdrive.
3Adaptability or versatility
If a diode circuit is used to achieve zero percent duty cycle, then the duty cycle control range is improved, but noise and temperature dependency increase
Solution Approach 1:
The patent extracts and eliminates the diode circuit from the PWM generation architecture. Instead of using diode-based methods to achieve zero percent duty cycle, the invention uses a clean electronic approach where the ramp signal is pre-charged to a non-zero level and the comparator naturally produces zero-width pulses when the control voltage intersects the ramp signal at the precharged level. This removal of the diode circuit eliminates the associated noise and temperature dependency while maintaining full duty cycle control range including zero percent capability.
4Speed
If the minimum pulse width is reduced, then the maximum switching frequency increases, but the conventional PWM circuit cannot maintain adequate overdrive
Solution Approach 1:
The patent implements preliminary charging of the ramp signal to a non-zero voltage level before each PWM comparison cycle. This precharge action ensures that when the minimum pulse width is reduced to enable higher switching frequencies, the ramp signal already has sufficient voltage differential to drive the comparator with adequate overdrive. The preliminary voltage preparation creates a head-start condition that maintains comparator reliability even as the available pulse width shrinks for high-frequency operation.
Data Source
AI summary
The rising edge of a pulse width modulated output signal occurs after an input ramp signal starts to rise. The ramp signal starts to rise after the rising edge of a periodic set signal and before the falling edge of a periodic set signal. A feedback control signal intersects a substantially linear region of the ramp signal to generate a reset signal using a PWM comparator. The periodic set signal and reset signal are input to a latching circuit to generate the pulse width modulated output signal. The minimum pulse width can approach zero while having adequate overdrive to the PWM comparator. Having the rising edge of the reset signal rise before the falling edge of the set signal can allow a zero percent duty cycle without the need for a ramp offset voltage.