Time-Encoding PWM Modulator With Counter-Based Linearization
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Solution Overview
Problem
Conventional time-encoding modulators, particularly those using asynchronous sigma-delta modulators, face challenges with high power consumption and large op-amp requirements, which are undesirable for battery-powered devices and audio applications requiring low power operation and improved linearity.
Innovation Solution
A time-encoding modulator comprising a controlled oscillator, an accumulator, and a hysteretic comparator, where the oscillator driving signal is based on a combination of an input signal and feedback, and the accumulator provides a value based on the number of pulses, allowing for differential PWM signal generation with reduced power consumption and improved linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an asynchronous sigma-delta modulator with large integrator capacitors and high-power op-amps is used to achieve acceptable linearity for audio applications, then the linearity performance is improved, but the power consumption increases and circuit area increases
Solution Approach 1:
The patent extracts the integration function from the traditional op-amp based integrator and implements it using a counter-based digital integration approach. The integrator capacitors and high-power op-amps are removed and replaced with a counter that accumulates oscillator pulse counts, significantly reducing power consumption and circuit area while maintaining the necessary integration function for audio signal processing
Solution Approach 2:
The patent replaces the analog mechanical integration system (op-amps with capacitors) with a digital counting system. The continuous analog integration process is substituted with discrete digital pulse counting, where the counter accumulates the number of oscillator pulses to achieve the same integration effect with much lower power consumption and simpler circuitry
2Use of energy by moving object
If a VCO based ADC with ring oscillator is used to achieve low power operation and small circuit area, then power consumption is reduced and circuit area is reduced, but the linearity deteriorates
Solution Approach 1:
The patent segments the ADC into distinct functional blocks: a time-encoding modulator that converts the analog input to a PWM signal with improved linearity, and a counter that measures the PWM duty cycle. This segmentation allows the VCO-based low-power architecture to be combined with a separate linearization stage, achieving both low power consumption and improved linearity through modular design
Solution Approach 2:
The patent introduces a time-encoding modulator as an intermediary between the analog input signal and the VCO-based counter. This modulator converts the analog signal into a PWM signal that linearizes the transfer function, acting as a mediator that prepares the signal in a form that the simple VCO counter can process accurately, thereby improving overall linearity without adding complex circuitry
3Manufacturing precision
If conventional ASDM with large integrator capacitors is used to achieve acceptable audio performance, then the audio quality is improved, but the circuit area increases
Solution Approach 1:
The patent extracts and removes the large integrator capacitors from the circuit, replacing the analog integration function with a digital counter-based approach. This extraction eliminates the need for large capacitor areas while maintaining the integration function necessary for audio signal processing, significantly reducing the overall circuit area
Solution Approach 2:
The patent uses a digital counter to copy and accumulate the functional effect of the analog integrator. Instead of physically implementing large capacitors, the system uses digital pulse counting to replicate the integration behavior, achieving the same audio processing capability with much smaller circuit area through functional equivalence
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed modulator achieves efficient and linear signal encoding with reduced power consumption, suitable for battery-powered devices and audio applications, by using current-controlled oscillators and a hysteretic comparator to generate PWM signals, thereby improving the linearity and efficiency of analogue-to-digital conversion.
Implementation Method 1
a first controlled oscillator configured to receive a first oscillator driving signal and output a first oscillation signal
Implementation Method 2
a hysteretic comparator configured to output either a first output state or a second output state and to alternate between said first and second output states based on a hysteretic comparison of said accumulator value with a defined reference
Data Source
AI summary
This application relates to modulators for providing time-encoded signals and in particular PWM signals. A modulator (200) has a first controlled oscillator (201P) configured to receive a first oscillator driving signal and output a first oscillation signal (S1). An accumulator (204) is configured to provide an accumulator value (VAL) based on a number of pulses of the first oscillation signal and a hysteretic comparator (205) alternates between first and second output states based on a hysteretic comparison of the accumulator value with a defined reference (REF). The first oscillator driving signal is based on a combination of an input signal and a feedback signal derived from an output of the hysteretic comparator. A second controlled oscillator (201N) may be configured to receive a second oscillator driving signal and output a second oscillation signal (S2) and the accumulator may provide the accumulator value based on a difference in the number of pulses of the first oscillation signal and the second oscillation signal.