Pulse-Width Modulated One-Wire Interface for High-Speed Serial Data
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Solution Overview
Problem
Current serial communication systems face challenges in increasing data rates without raising bus clock frequency or modifying encoding, particularly in mobile communication devices with complex applications, where traditional protocols like I2C, I3C, and RFFE struggle with high-priority and real-time message handling due to latency and interference issues.
Innovation Solution
The implementation of a method that transmits pulse-width modulated datagrams over a serial bus, using a one-bit sequence start condition with a first edge initiating the datagram and a second edge indicating an optimal sampling point, allowing for command and payload fields to be transmitted efficiently, enabling robust decoding and reduced latency without increasing clock frequency, and supporting communication over a single wire using RFFE protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional serial bus protocols (I2C, I3C, RFFE) are used, then device compatibility and ease of operation are maintained, but data throughput is limited and latency increases for high-priority messages
Solution Approach 1:
The patent changes the encoding parameter from traditional voltage-level encoding to pulse-width modulation (PWM). Each data bit is represented by a pulse whose width encodes the data value, allowing for more efficient data transmission. The start condition uses a specific pulse width (e.g., 2.5ms) that is distinct from data pulses, enabling clear frame delimitation without additional clock signaling.
Solution Approach 2:
The patent extracts and removes the separate clock signal from the traditional two-wire I2C interface, reducing it to a single-wire PWM-based interface. The clock function is implicit in the pulse timing and width, eliminating the need for a dedicated clock line and reducing bus complexity while maintaining synchronization.
2Productivity
If bus clock frequency is increased to raise data throughput, then data rate improves, but power consumption increases and signal integrity deteriorates
Solution Approach 1:
The patent employs periodic pulse-width modulated signals where each data bit is transmitted as a regular pulse with width proportional to the data value. This periodic structure with well-defined timing intervals (e.g., 100Hz base frequency with variable pulse widths) enables reliable sampling without requiring high clock frequencies, maintaining signal integrity while achieving efficient data transmission.
3Measurement precision
If explicit clock signals are used for synchronization, then timing precision is maintained, but device complexity and wiring requirements increase
Solution Approach 1:
The patent merges the clock and data functions into a single PWM signal on one wire. The timing information is embedded within the pulse widths themselves rather than being provided by a separate clock signal. This consolidation eliminates the need for separate clock wiring and reduces interface complexity while preserving synchronization through the inherent timing structure of the PWM encoding.
4Adaptability or versatility
If traditional encoding schemes are used, then compatibility with existing devices is maintained, but decoding complexity increases for PWM signals
Solution Approach 1:
The PWM encoding scheme is self-describing and self-synchronizing. Each pulse's width automatically indicates the data value, and the start condition's distinct pulse width (2.5ms) automatically delimits frames. The receiver can decode the signal by measuring pulse widths against a known reference without requiring complex state machines or additional synchronization protocols, simplifying the decoding process while maintaining versatility.
Data Source
AI summary
Increased data rates over a serial bus are enabled without increasing clock frequency. A method performed at a device coupled to a serial datalink includes transmitting a one-bit sequence start condition over a data wire of a datalink, providing a command field in the pulse-width modulated datagram, where a first-transmitted bit of the command field identifies the datagram as a write command directed to a register located at address zero, and providing data in a third-transmitted bit and subsequently-transmitted bits of the command field to be written to the register located at address zero when a second-transmitted bit of the command field has a first value. The sequence start condition has a first edge that commences transmission of a pulse-width modulated datagram and a second edge that indicates an optimal sampling point in each bit period of the pulse-width modulated datagram.