PWM Module Dynamic Phase Offset and Register Update
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Solution Overview
Problem
Existing digital and analog PWM generating devices lack the capability to dynamically adjust phase offset during operation, and they require multiple simultaneous duty cycle register updates, which is not feasible for advanced power supply applications.
Innovation Solution
A digital PWM generation module integrated with a digital processor that enables high-speed, high-resolution PWM generation with dynamically adjustable phase offset, simultaneous update of multiple PWM duty cycle registers, and automatic timing for ADC triggers, using a combination of adder modules, counter modules, and multiplexers to reduce processor workload.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a digital PWM generating device is designed with fixed phase relationships among multiple PWM outputs, then the device complexity is reduced and ease of manufacture is improved, but the adaptability to dynamically adjust phase offset during operation is lost
Solution Approach 1:
The patent implements dynamic phase offset adjustment by making the phase offset values programmable and changeable during operation. Each PWM channel has an associated phase offset register that can be written to at runtime, allowing the phase relationship between PWM outputs to be dynamically modified without changing the hardware configuration. This transforms a static design into a dynamic, reconfigurable system.
2Manufacturing precision
If multiple PWM duty cycle registers are updated independently, then the manufacturing precision and control accuracy are maintained, but the processor workload increases and productivity decreases
Solution Approach 1:
The patent merges multiple PWM duty cycle registers into a single unified duty cycle register. This single register is then time-multiplexed to serve multiple PWM channels sequentially. The PWM generator uses a multiplexer to route the duty cycle value from the single register to the appropriate PWM channel based on the current update phase, thereby reducing processor workload while maintaining accurate duty cycle control for all channels.
Solution Approach 2:
The patent implements periodic updating of multiple PWM duty cycle registers through a phased update mechanism. The single duty cycle register is updated in sequential phases for different PWM channels during each PWM period. This periodic, time-multiplexed approach ensures that each channel receives its correct duty cycle value at the appropriate time while reducing the overall processor burden compared to independent continuous updates.
3Speed
If high switching frequencies are used in PWM generation, then the power supply control response speed is improved, but the resolution of PWM signals decreases
Solution Approach 1:
The patent applies partial action by implementing fine-adjustment mechanisms that add sub-cycle resolution to the PWM generation. The system uses a base PWM period determined by the switching frequency, and then adds fine-adjustment counts that provide additional precision beyond the basic clock resolution. This allows high switching frequencies to be maintained while achieving higher effective resolution through the fine-adjustment capability.
Data Source
AI summary
A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.