PWM Amplifier Ramp Synchronization Without Separate PLLs

The patent combines multiple ramp generators into a single ramp generator that can dynamically switch between different voltage supplies (high voltage supply and low voltage supply). This single ramp generator produces a single ramp signal that is used by both Y-bridge drivers, eliminating the need for separate ramp generators and the associated master and slave PLL circuitry for synchronization, thereby reducing circuit space consumption while maintaining constant audio signal gain.

The single ramp generator is designed to perform multiple functions: it generates the ramp signal for PWM modulation and simultaneously provides the clock signal for both Y-bridge drivers. By making the ramp generator universal, the patent eliminates the need for separate clock generation circuits and PLLs, reducing overall circuit complexity and space requirements while ensuring synchronized operation of both drivers.

The patent merges the clock signal generation function into the single ramp generator. The ramp generator produces both the ramp signal and the clock signal used by both Y-bridge drivers. Since both drivers derive their clock signals from the same source (the single ramp generator), phase and frequency offsets are eliminated, ensuring constant audio signal gain even when switching between high and low voltage supplies.

The patent incorporates a loop filter that receives feedback from the output signals of both Y-bridge drivers. This feedback mechanism allows the system to monitor and adjust the ramp signal characteristics to maintain constant audio signal gain when switching between voltage supplies, compensating for any variations without requiring separate PLL circuitry.