PWM Receiver Clock Recovery Without Sync Bits
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Solution Overview
Problem
Memory systems face challenges in reducing power consumption while maintaining accurate data transmission, as slowing clock speed decreases operation efficiency and removing clocks introduces significant jitter that can cause data errors, and existing solutions like phase lock loops require synchronization bits that reduce data rate.
Innovation Solution
A pulse width demodulation method that derives a clock signal from the data itself without sync-bits, using dual paths at half operation rates, with integrator legs and comparators to process differential signals and generate clock signals, allowing for jitter correction and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If accurate clocks are used to synchronize data flow, then data transmission accuracy is improved, but power consumption increases
Solution Approach 1:
The system uses the data signal itself to provide timing information through pulse width modulation, eliminating the need for separate clock signals. The data signal carries both information and timing cues, allowing the receiver to self-synchronize without external clock assistance, thus reducing power consumption while maintaining accuracy.
Solution Approach 2:
The invention employs periodic pulse width modulated signals where the width of each pulse encodes timing information. This periodic structure provides regular synchronization points without requiring continuous high-power clock signals, enabling the system to maintain synchronization with lower power expenditure.
2Use of energy by moving object
If clock speed is slowed to reduce power consumption, then power usage decreases, but operation efficiency deteriorates
Solution Approach 1:
The system uses periodic pulse width modulated signals where timing information is encoded in the pulse widths rather than relying on high-speed continuous clocking. This allows the system to operate at lower clock speeds while maintaining accurate timing through the periodic pulse structure, thus reducing power consumption without sacrificing operational efficiency.
3Use of energy by moving object
If clocks are removed to achieve low power transmission, then power consumption decreases, but jitter increases causing data errors
Solution Approach 1:
The data signal itself provides timing reference information through its pulse width modulation, eliminating dependency on external clock signals that would be prone to jitter. The receiver extracts timing information directly from the data signal's inherent structure, maintaining synchronization accuracy without requiring power-hungry clock circuits.
Solution Approach 2:
The system incorporates timing recovery mechanisms that continuously monitor the pulse width modulated signal and adjust the receiver's timing reference accordingly. This feedback loop compensates for any timing variations or jitter in the received signal, maintaining data accuracy even without stable external clocking.
4Reliability
If phase lock loops are used to correct jitter, then timing accuracy is improved, but data rate decreases due to synchronization bits
Solution Approach 1:
The pulse width modulated data signal inherently contains timing information that enables the receiver to self-synchronize without requiring separate synchronization bits. The timing recovery is achieved by analyzing the pulse width variations in the data signal itself, eliminating the need for additional overhead bits that would reduce the effective data rate.
Data Source
AI summary
A method for improving timing between solid state devices, e.g., in non-volatile memory device is described and includes generating timing signals from the data stream so that the data stream is free from synchronization bits. The PWM data stream is converted from CML to CMOS level. An even decoder decodes the even data signal. An odd decoder decodes the odd signal. The decoders rely on the respective signal, even or odd, to increase past a slower rising signal based on both the odd and even signals to change from a default low state to a high state. The clock signal is derived from edges of the data itself.