PWM Clock and Data Receiver with Peak-Detected Comparator Biasing
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Solution Overview
Problem
Conventional telecommunication systems face challenges with expensive commercial ICs that introduce clock jitter and wander, and discrete analog circuits struggle to optimize for various types of timing signals, necessitating a cost-effective and versatile receiver circuitry for data and timing information recovery.
Innovation Solution
A PWM clock and data receiver with comparators and a PWM control element generates fixed frequency, variable duty cycle control signals to bias comparators, optimizing clock and data recovery by performing peak detection and adjusting duty cycles based on detected peak levels, enabling efficient recovery of data and timing information from diverse signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If commercial ICs are used for data signal reception, then reliable data and timing recovery is achieved, but cost increases and clock jitter and wander are introduced
Solution Approach 1:
The patent replaces commercial IC-based clock and data recovery systems with a custom-built receiver circuit using discrete analog components (comparators, resistors, capacitors, logic gates). This substitution eliminates the clock jitter and wander inherent in commercial ICs while maintaining reliable data and timing recovery through carefully designed analog signal processing circuits
Solution Approach 2:
The patent employs inexpensive discrete analog components instead of expensive commercial ICs. The receiver uses multiple comparators, resistors, capacitors, and logic gates that are individually cheap and can be easily replaced or adjusted, providing a cost-effective solution that avoids the harmful effects of integrated circuits
2Ease of manufacture
If discrete analog circuits with fixed comparators are used, then cost is reduced, but optimization for various timing signals becomes difficult
Solution Approach 1:
The patent implements dynamic adjustability in the discrete analog circuit by providing variable reference voltage inputs to the comparators and adjustable threshold levels. This allows the receiver to be optimized for different timing signal types (DS1, E1, etc.) by changing the reference voltages and threshold settings, making the fixed discrete circuit adaptable to various signal standards without requiring redesign
Solution Approach 2:
The patent designs a universal receiver circuit that can handle multiple timing signal types through configurable comparator thresholds and reference voltages. The same basic discrete analog circuit architecture serves multiple functions by adjusting the reference levels and bias voltages, enabling it to process DS1, E1, and other timing signals with a single design
3Measurement precision
If multiple data slicing comparators and peak level detection comparators are used, then decision process accuracy is improved, but circuit complexity increases
Solution Approach 1:
The patent divides the signal processing function into multiple specialized comparator stages: peak level detection comparators that first identify signal peaks, and data slicing comparators that then make data decisions based on those peaks. This segmentation of the decision process into distinct functional blocks improves accuracy while keeping each individual comparator relatively simple
Solution Approach 2:
The patent performs peak level detection as a preliminary action before data slicing decisions are made. The peak level comparators first detect and establish the peak voltage levels of the incoming signal, which then provides reference information for the data slicing comparators to make accurate decisions. This preliminary peak detection simplifies the subsequent data decision process
Data Source
AI summary
The present disclosure generally relates to pulse width modulation (PWM) clock and data receivers and methods for recovering data and timing information from received signals. A PWM clock and data receiver in one exemplary embodiment of the present disclosure has comparators for detecting pulses of a received data signal. The PWM clock and data receiver provides fixed frequency, variable duty cycle control signals that are used to control the biasing of the comparators to establish data decision levels for clock and data recovery. At times, the output of at least one comparator is used to perform peak detection, and the receiver controls the duty cycles of the control signals based on such peak detection in an effort to optimize the clock and data recovery process.