PWM Controller Using Sigma-Delta Modulator to Reduce ADC Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional control circuits for pulse width modulated (PWM) signals in power converter circuits, such as DC-DC boost converters, face challenges in adjusting duty cycles efficiently and require analog to digital converters, leading to latency and increased costs.
Innovation Solution
A control circuit that includes an analog processing component with a sigma-delta modulator to generate a quantized output based on feedback and reference signals, and a digital processing component using a digital filter to adjust the PWM duty cycle, eliminating the need for a complete ADC and allowing for synchronous operation with reduced latency and predictable interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional control circuits use analog to digital converters (ADC) to process feedback signals, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts only the essential quantization function from a complete ADC, using a sigma-delta modulator that generates quantized output directly from the feedback signal without requiring full ADC functionality. This reduces device complexity while maintaining sufficient measurement precision for PWM control applications.
Solution Approach 2:
The patent replaces expensive, complex ADC components with simpler, cheaper alternatives including a sigma-delta modulator and digital filter combination that achieves equivalent or sufficient functionality at lower cost and complexity for the specific application requirements.
2Adaptability or versatility
If conventional control circuits use microcontrollers executing software, then adaptability is improved, but latency increases
Solution Approach 1:
The patent replaces software-based microcontroller processing with a hardware-based digital filter implementation. This substitution eliminates software execution overhead and ADC requirements, achieving the same adaptability through hardware logic with significantly reduced latency of less than two clock cycles.
3Ease of operation
If conventional control circuits adjust duty cycle by varying on-time or off-time, then ease of operation is improved, but frequency stability deteriorates
Solution Approach 1:
The patent uses a clock-synchronized periodic sampling approach where the digital filter processes feedback signals at fixed clock intervals. This ensures that PWM frequency remains constant and predictable while still allowing easy duty cycle adjustment through the accumulated digital filter output that directly controls the PWM generator.
Data Source
AI summary
A control circuit adjusts the duty cycle of a PWM control signal. An analog processing component within the control circuit receives an analog feedback input signal and compares it to an analog reference signal to generate a pre-processed signal. A sigma-delta modulator within the analog processing component generates a quantized signal based on the pre-processed signal. A digital processing component stores a value. The controller then adjusts the duty cycle of the PWM signal to correspond to the value. A clock keeps the system synchronized.


