High-Resolution PWM Signal Generation Circuit
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Solution Overview
Problem
Conventional PWM signal generation circuits face challenges in generating high-resolution signals due to large minimum unit changes in duty cycle, making it difficult to finely control output power and achieve high-performance power supplies, especially with low-resolution PWM signals and analog feedback circuits.
Innovation Solution
A high-resolution PWM signal generation circuit and method that constructs a delay array corresponding to a 0.5 clock time period, samples PWM signals, and compensates for delay variations using a buffer device, incorporating an integer part pulse generation circuit and a fractional part pulse generation circuit to determine overflow and achieve desired duty resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional counter and comparison circuit method is used to generate PWM signals, then the circuit structure is simple, but the minimum unit of duty cycle change is large (one clock period), making it impossible to achieve high-resolution control
Solution Approach 1:
The PWM signal generation is divided into two independent parts: integer part pulse generation circuit and fractional part pulse generation circuit. The integer part uses a counter to generate the base PWM signal, while the fractional part uses a delay array to generate fine-resolution adjustments. This segmentation allows high-resolution control without requiring a complete redesign of the PWM generation mechanism.
Solution Approach 2:
The patent introduces a time-domain dimension by using a delay array that provides delay times corresponding to 0.5 clock periods. This additional temporal dimension allows for fine-resolution duty cycle control between the clock edges, effectively increasing the resolution beyond what a single counter can achieve.
2Manufacturing precision
If the clock frequency is increased to reduce the minimum duty cycle change unit, then the PWM resolution improves, but the system becomes more sensitive to noise and the area usage increases
Solution Approach 1:
The patent dynamically selects between different delay values (0.5 clock period, 0.25 clock period, etc.) based on the required resolution. The delay array can adaptively adjust its delay time according to the fractional part of the duty cycle, providing fine control without requiring a high fixed clock frequency, thus reducing noise sensitivity.
3Manufacturing precision
If a delay array corresponding to 0.5 clock time period is constructed, then high-resolution PWM signals can be generated, but the delay variation due to process or temperature changes affects the accuracy
Solution Approach 1:
The patent incorporates a feedback mechanism where the actual delay time is monitored and compared with the ideal delay time. Based on this comparison, the system adjusts the selected delay value from the delay array to compensate for process or temperature variations, ensuring accurate PWM duty cycle control despite environmental changes.
4Manufacturing precision
If both the period and logic H time of PWM signal are arbitrarily changed at time intervals of 1/2 of a clock period, then the resolution is improved over a wide duty cycle range, but it becomes difficult to generate high-resolution PWM signals without a control loop
Solution Approach 1:
The patent makes the PWM signal generation self-sufficient by integrating both integer and fractional part generation within a single synchronous circuit. The system automatically selects appropriate delay values from the delay array based on the fractional part of the duty cycle, eliminating the need for external control loops while maintaining high resolution across the entire duty cycle range.
Data Source
AI summary
A pulse width modulation (PWM) signal generation circuit and method are disclosed herein. The PWM signal generation circuit includes an integer part pulse generation circuit, and a fractional part pulse generation circuit. The integer part pulse generation circuit generates an integer part pulse using the integer part of the digitized value of a duty cycle, i.e., the ratio of the time during which any one of high and low levels is maintained to the period of a PWM signal. The fractional part pulse generation circuit generates the PWM signal using the integer part pulse and the fractional part of the digitized value of the duty cycle.