PWM Switching Circuit for Ternary-Quaternary Modulation Control

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Solution Overview

Problem

Conventional class-D amplifiers face inefficiencies in power consumption due to fixed duty cycles, leading to unnecessary charging of LC circuits and increased power consumption when switching between ternary and quaternary modulations.

Innovation Solution

A switching circuit and method that dynamically adjust duty cycles by using computing circuits with shifters, adders, multiplexers, and subtractors to generate output signals for PWM signals, allowing for variable duty cycles and reducing power consumption by shortening charging times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a fixed duty cycle of 50% is used for PWM signals, then the modulation structure is simple, but power consumption increases due to unnecessary charging of LC circuits

Engineering Contradiction:
Improvemodulation structureVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic duty cycle adjustment by using computing circuits (adders, subtractors, shifters) to calculate variable duty cycles based on input signal amplitude. The duty cycle transitions from a fixed 50% to a dynamic value that varies with the input signal, allowing the LC circuits to be charged only when necessary and reducing unnecessary power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the duty cycle parameter from a fixed value (50%) to a variable parameter that adapts to the input signal characteristics. By computing the duty cycle as (input signal + duty signal) / 2 or (duty signal - input signal) / 2 depending on polarity, the system optimizes power consumption while maintaining correct modulation.

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If ternary modulation is used for large duty cycles, then power consumption is reduced, but total harmonic distortion increases compared to quaternary modulation

Engineering Contradiction:
Improvepower consumptionVSAvoidtotal harmonic distortion
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent dynamically switches between ternary and quaternary modulation modes based on the input signal characteristics and duty cycle requirements. The computing circuits enable flexible generation of PWM signals that can adapt to different modulation modes, allowing the system to achieve low power consumption when using ternary modulation for large duty cycles while maintaining low THD by switching to quaternary modulation when needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the modulation mode parameter dynamically based on operating conditions. By computing different output signals based on the input signal polarity and magnitude, the system can switch between ternary (more power-efficient) and quaternary (lower THD) modulation modes, optimizing both power consumption and signal quality.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If quaternary modulation is used for small duty cycles, then total harmonic distortion is reduced, but power consumption increases

Engineering Contradiction:
Improvetotal harmonic distortionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic mode selection that switches between quaternary and ternary modulation based on the current operating point. The computing circuits calculate the appropriate modulation mode and duty cycle in real-time, allowing the system to use quaternary modulation for small duty cycles when low THD is critical while minimizing power consumption by using ternary modulation when appropriate.

Inventive Principle:
Principle #15Dynamics

4Use of energy by moving object

If variable duty cycles are implemented, then power consumption is reduced, but device complexity increases due to additional computing circuits

Engineering Contradiction:
Improvepower consumptionVSAvoidcomputing circuit structure
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent segments the computing function into separate dedicated circuits: adders for positive polarity processing, subtractors for negative polarity processing, and shifters for duty cycle adjustment. This segmentation allows each circuit to perform its specific function efficiently, reducing the overall complexity compared to a general-purpose processor while still achieving variable duty cycle control.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent replaces complex control logic with straightforward arithmetic operations (addition, subtraction, bit-shifting) that can be implemented with simple digital circuits. This substitution of mechanical/control complexity with basic mathematical operations reduces the overall device complexity while maintaining the capability for dynamic duty cycle adjustment.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11489499B1Circuit and method for switching between ternary modulation and quaternary modulation
Publication Date: 2022.11.01 ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
  • US11489499B1 patent drawing
  • US11489499B1 patent drawing
  • US11489499B1 patent drawing

AI summary

A switch circuit provides a first output signal and a second output signal for switching between ternary modulation and quaternary modulation for a target device. A first output signal is provided from one of a first signal, a second signal and a ground signal according to an input signal and a duty signal, wherein the first signal is generated through performing a one-bit left-shift operation for the input signal, and the second signal is generated through adding the input signal and the duty signal. A second output signal is provided from one of a third signal, a fourth signal and the ground signal according to the input signal and the duty signal, wherein the third signal is generated through subtracting the input signal from the duty signal, and the fourth signal is generated through performing a two's-complement transformation and the one-bit left-shift operation for the input signal.