PWM Synchronization via Local Clock Segmentation
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Solution Overview
Problem
Existing methods for synchronizing multiple power supplies, such as driving all power supplies with a common clock, face issues like noise interference, unpredictable transitions, and failure in the event of a lost sync signal, leading to inefficiencies and potential device malfunction.
Innovation Solution
A method where the master circuit provides a synchronization signal indicating a reference point in the PWM cycle to the slave device, allowing the slave to adjust its internal clock frequency and phase to match the master's, using a single sync signal for frequency and phase lock, enabling synchronization in a 3-stage process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common clock signal is used to drive all power supplies, then synchronization is achieved, but noise interference and signal degradation occur over significant distances
Solution Approach 1:
The patent extracts the clock generation function from a centralized common clock source and distributes individual clock circuits to each power supply device. Each device generates its own clock signal locally, eliminating the need for long-distance clock signal transmission and the associated noise interference while maintaining synchronization through a different mechanism.
Solution Approach 2:
The patent introduces a sync signal as an intermediary mechanism. Instead of directly transmitting clock signals over long distances, a low-frequency sync signal is transmitted from master to slave devices, which then use their own local clock circuits to generate synchronized PWM outputs based on the timing information from the sync signal.
2Reliability
If the clock frequency of the master is reduced by an integer divisor to generate a sync signal, then synchronization is achieved, but the slave circuit fails to function if the sync signal is lost
Solution Approach 1:
The patent implements dynamic operation modes for the slave circuit. The slave can operate in synchronized mode when a valid sync signal is present, and automatically switch to independent free-running mode when the sync signal is lost or invalid. This dynamic adaptability ensures continuous operation under varying conditions.
Solution Approach 2:
The slave circuit maintains its own independent clock circuit and PWM generation capability. When the sync signal is lost, the slave uses its own local clock to continue generating PWM signals, ensuring that the power supply function is not interrupted. The slave essentially serves itself when the master synchronization is unavailable.
3Reliability
If a switch between slave clock and master clock signal is implemented, then synchronization is achieved, but unpredictable transitions and glitches occur at the time of switchover
Solution Approach 1:
The patent performs preliminary frequency matching before phase alignment. The slave circuit first adjusts its clock frequency to match the master's frequency while both operate independently, ensuring frequency synchronization. Only after frequency matching is achieved does the system proceed to phase alignment using the sync signal, preventing glitches that would occur with direct switching without preliminary preparation.
Solution Approach 2:
The patent implements a dynamic three-stage synchronization process that progressively transitions from independent operation to synchronized operation. The stages are: 1) Independent free-running mode, 2) Frequency matching mode with continuous independent operation, and 3) Phase-locked synchronized mode. This gradual dynamic transition eliminates unpredictable glitches associated with direct switching.
4Productivity
If multiple power supply devices are provided on a single circuit board, then lower voltage and increased efficiency are achieved, but synchronization problems such as beat frequencies and large output current ripple occur
Solution Approach 1:
The patent segments the clock generation function into independent local clock circuits in each power supply device, rather than using a single centralized clock. This segmentation allows each device to operate independently with its own clock source, preventing the beat frequencies and current ripple issues that arise from shared clock sources while maintaining synchronization through the sync signal mechanism.
Data Source
AI summary
The present disclosure is directed generally to switch mode power supplies operating in a master-slave configuration and provides a method of synchronizing the PWM outputs from the master and slave devices to avoid problems such, for example, as the generation of beat frequencies.