PWM Timer Architecture Using DLL Edge Shifting for Fine Resolution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current microcontrollers cannot generate high enough clock frequencies to achieve accurate Pulse Width Modulation (PWM) signal frequencies with high resolution, particularly at switching frequencies above hundreds of megahertz, limiting the accuracy of control loops in applications like motor control and digital power conversion.
Innovation Solution
A timer is divided into two stages: a low accuracy stage and a high accuracy stage, where the low accuracy stage generates a PWM signal based on a relatively low-speed clock, and the high accuracy stage time shifts the signal using a Delay-Locked Loop (DLL) to achieve a higher frequency resolution, allowing for precise PWM signal generation without requiring high-frequency components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a timer runs at maximum possible speed to achieve high PWM frequency resolution, then the PWM frequency resolution is improved, but the device complexity and manufacturing cost increase due to requiring high-frequency clock generation (3.2 GHz for 14-bit resolution at 200 kHz)
Solution Approach 1:
The timer is divided into two independent stages: a low accuracy stage that generates PWM signals at lower frequencies using standard clock speeds, and a high accuracy stage that applies fine-grained time-shifting to achieve high resolution. This segmentation allows each stage to operate within feasible frequency ranges while collectively achieving 14-bit resolution without requiring 3.2 GHz clock generation.
Solution Approach 2:
A delay-locked loop (DLL) is introduced as an intermediary mechanism between the low accuracy PWM generator and the final high-resolution output. The DLL provides precise time-shifting capability that enhances the base PWM signal's resolution without requiring the entire system to operate at high frequencies, thus resolving the contradiction between resolution and device complexity.
2Measurement precision
If full custom logic is implemented to achieve gigahertz-range operation for high resolution PWM, then the PWM frequency resolution is improved, but the manufacturing cost increases significantly
Solution Approach 1:
By segmenting the timer into two stages with different accuracy requirements, the system avoids the need for expensive full custom gigahertz-range logic. The low accuracy stage can use standard CMOS processes, while the high accuracy stage uses a DLL that provides fine resolution without requiring custom high-frequency logic design, thereby reducing manufacturing costs.
Solution Approach 2:
The invention changes the operational parameters from requiring uniform high-frequency operation across the entire timer to using low-frequency operation with precise time-shifting. This parameter change allows the use of standard manufacturing processes rather than expensive custom gigahertz logic fabrication.
3Device complexity
If a single-stage timer is used for PWM generation, then the device complexity is reduced, but the PWM frequency resolution is insufficient at high switching frequencies
Solution Approach 1:
The timer is segmented into two functional stages: a low accuracy stage for generating the base PWM signal and a high accuracy stage for applying precise time-shifting. This segmentation enables the system to achieve high resolution without excessively complicating the overall device structure, as each stage has a specialized function.
Solution Approach 2:
The invention merges two different timing approaches (low accuracy direct generation and high accuracy time-shifting) into a unified timer structure. This combination allows the system to achieve high-resolution PWM generation while maintaining a relatively simple overall device structure compared to using a single complex high-frequency timer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the generation of PWM signals with high accuracy and flexibility, allowing for a wide range of timer clock frequencies without the need for high-frequency digital logic, resulting in improved control loop accuracy and scalability.
Implementation Method 1
the high accuracy stage time shifts the signal using a Delay-Locked Loop (DLL) to achieve a higher frequency resolution
Data Source
AI summary
A timer including a Pulse Width Modulation (PWM) signal generator configured to generate, based on a clock, a PWM signal having a first frequency resolution; a PWM time shifter configured to receive from the PWM signal generator the PWM signal having the first frequency resolution, and output a PWM signal having a second frequency resolution, wherein the second frequency resolution is higher than the first frequency resolution; and a control monitor configured to: control the PWM time shifter to time shift rising edges or falling edges of the PWM signal by an amount corresponding with a second frequency resolution.