PWM Timer RAM Duty Updates for Reliable Microcomputer Pulses
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Solution Overview
Problem
In microcomputers, the bus traffic overload leads to temporary traps in the CPU, affecting the generation and reliability of PWM pulses, especially due to software errors or hardware breakdowns, resulting in incomplete PWM output.
Innovation Solution
Incorporating a PWM timer with a RAM for storing duty values and multiple PWM controllers that count up from initial values, allowing duty value changes without CPU intervention, thus avoiding bus traffic overload and ensuring reliable PWM pulse generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CPU controls the PWM duty value through bus traffic, then the PWM pulse can be generated, but the bus traffic overload causes temporary traps in the CPU and reduces reliability
Solution Approach 1:
The patent divides the PWM control function into two independent parts: the CPU sets initial duty values through bus traffic, while the PWM timer autonomously updates duty values using its own counter and comparison logic. This segmentation reduces CPU bus traffic load and eliminates temporary traps while maintaining PWM generation reliability.
Solution Approach 2:
The PWM timer is designed to autonomously update duty values without CPU intervention. The counter increments automatically, compares with stored duty values, and triggers updates independently, allowing the system to serve itself and reducing dependency on CPU bus traffic.
2Reliability
If the CPU continuously updates duty values, then the PWM pulse can adapt to changing requirements, but software errors or hardware breakdowns can cause interruption failures and reduce reliability
Solution Approach 1:
The PWM timer autonomously manages duty value updates through its internal counter and comparison mechanism, eliminating the need for CPU intervention during operation. This self-service capability ensures continuous reliable PWM generation even when CPU software or hardware fails.
Solution Approach 2:
The CPU performs preliminary action by setting initial duty values in the PWM timer before autonomous operation begins. This preliminary configuration allows the PWM timer to function independently thereafter, reducing operational dependency on the CPU.
3Productivity
If the PWM timer operates autonomously without CPU intervention, then bus traffic overload is avoided, but the initial design requires CPU configuration
Solution Approach 1:
The CPU performs preliminary configuration by setting initial duty values and control parameters in the PWM timer before autonomous operation. This one-time preliminary action enables high-speed autonomous PWM updates without ongoing CPU intervention, balancing initial complexity with ongoing productivity.
Data Source
AI summary
A microcomputer includes: a CPU executing a predetermined calculation process; and a PWM timer generating a PWM pulse. The PWM timer includes a RAM for storing a duty value of the PWM pulse and a PWM controller for generating the PWM pulse. The PWM controller includes a PWM counter for counting up from a predetermined value as an initial value. The PWM pulse has an unit waveform, which is generated based on comparison between the duty value of the RAM and an output value of the PWM counter. The RAM outputs a new duty value at every comparison without functioning the CPU so that the duty value of the PWM pulse is changed in chronological order.