PWM Signal Generating Circuit for Voltage Error Compensation
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Solution Overview
Problem
Conventional PWM signal generation techniques for power converters face challenges in accurately compensating for voltage errors caused by dead time and switching element delays, leading to output voltage mismatches and increased operational loads, particularly due to the need for hardware circuits and complex software processing.
Innovation Solution
A semiconductor integrated circuit with a PWM signal generating system that includes a counter for pulse width measurement, a register for synchronization, and an A/D conversion system for digital signal processing, allowing for cyclic software processing to manage PWM signal timing and compensate for voltage errors while minimizing hardware additions and software operation loads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If compensation for dead time and switching delay is implemented using conventional hardware circuits or complex software processing, then voltage error compensation precision is improved, but device complexity and operational load increase
Solution Approach 1:
The patent combines the counter function, register function, and A/D conversion function into a single semiconductor integrated circuit. This merging eliminates the need for separate external hardware circuits while maintaining precise voltage error compensation capability, thereby reducing device complexity without sacrificing measurement precision
Solution Approach 2:
The semiconductor integrated circuit performs multiple functions including PWM signal generation, voltage error detection, A/D conversion, and dead time compensation all within a single device. This multi-functionality reduces the overall system complexity by eliminating dedicated separate circuits for each function while maintaining high precision compensation
2Manufacturing precision
If feedback-based compensation systems are implemented, then output voltage accuracy is improved, but device complexity and operational load increase
Solution Approach 1:
The patent integrates the feedback mechanism directly into the semiconductor integrated circuit by combining the A/D conversion system with the PWM control logic. This allows the feedback system to operate within a single device rather than requiring separate external circuits, reducing complexity while maintaining output voltage accuracy
Solution Approach 2:
The semiconductor integrated circuit automatically performs feedback-based compensation without requiring external intervention or complex external circuitry. The internal counter and register system automatically adjusts PWM signals based on detected voltage errors, enabling self-service compensation that reduces overall system complexity
3Speed
If preset compensation amounts are used, then compensation speed is improved, but compensation precision deteriorates due to mismatch with actual switching element performance
Solution Approach 1:
The patent implements real-time feedback by detecting the actual output voltage through the A/D conversion system and using this information to dynamically adjust PWM signals. This feedback mechanism eliminates the mismatch problem of preset compensation by continuously adapting to actual switching element performance, achieving both speed and precision
Solution Approach 2:
The compensation system transitions from static preset values to dynamic real-time adjustment. The counter and register system continuously monitors actual switching behavior and adjusts compensation amounts dynamically, enabling the system to adapt to varying operating conditions while maintaining both speed and precision
Data Source
AI summary
Provided is a control technique of a PWM conversion type power converter capable of compensating for a voltage error due to voltage drop mainly at a switching element and managing a switching time of a PWM signal at the same time, and capable of suppressing increase/decrease of software operation load and addition of a hardware circuit to the minimum. A semiconductor integrated circuit having a PWM signal generating unit which generates a PWM signal is provided with a PWM timer unit including a counter counting a pulse width of a pulse signal inputted from the outside with delay from a PWM signal, a register loading a counter value of the counter in synchronization with the PWM signal, and an A/D converting unit converting an analog signal serving as a source signal of the pulse signal inputted from the outside to a digital signal.