Pulse-Width-to-Voltage Duty Cycle Detection for PVT-Stable Clocks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Maintaining a high-speed clock signal with a 50% duty cycle throughout an integrated circuit system is challenging due to noise and process, voltage, and temperature variations, which can only be guaranteed with additional circuitry like duty cycle detectors and correctors.
Innovation Solution
A duty cycle adjuster system comprising a duty cycle corrector, counter, and detector, along with a pulse-width-to-voltage converter, which adjusts the clock signal's duty cycle by converting pulse width to control voltage to regulate the ring oscillator's frequency, mitigating PVT errors and ensuring a 50% duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional circuitry such as duty cycle detectors and correctors is used to adjust the duty cycle, then the duty cycle accuracy is improved, but the device complexity increases
Solution Approach 1:
The duty cycle detector circuit uses the clock signal itself and its inverted version to generate the duty cycle detection signal, without requiring external reference signals or additional complex circuitry. The circuit serves itself by utilizing available signals within the system to achieve duty cycle measurement and correction.
2Reliability
If duty cycle detectors and correctors are added to account for PVT errors, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The duty cycle detector generates a duty cycle detection signal that feeds back to indicate when duty cycle correction is needed. This feedback mechanism allows the system to automatically adjust and maintain proper duty cycle without complex external control systems, improving reliability through self-correction.
3Productivity
If high-speed clock signals are distributed throughout the IC system, then the productivity is improved, but the duty cycle stability deteriorates due to noise and PVT variations
Solution Approach 1:
The system segments the clock signal distribution by providing separate clock and inverted clock signals to different parts of the circuit, with the duty cycle detector monitoring and correcting duty cycle variations in each segment independently. This allows high-speed distribution while maintaining stability through localized correction.
Data Source
AI summary
A pulse-width-to-voltage (“PWV”) converter, comprises: a switch, a capacitor, a current source, and a current sink. The switch is operable by a signal. The current source, the current sink, and the switch are serially connected across a high voltage potential and a low voltage potential. An output node is coupled to a serial connection between the current source and the current sink. An end of the capacitor is coupled to the output node for converting a current into a control voltage indicative of a duty cycle of the signal.