Pyramidal Flow Placement for Circuit Block Legalization
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Solution Overview
Problem
Existing methods for circuit block legalization in integrated circuits, such as FPGAs and structured ASICs, face challenges in efficiently minimizing displacement while adhering to density and floorplan constraints, with geometric sorting methods being inaccurate and flat graph-based approaches being slow and runtime expensive.
Innovation Solution
A pyramidal network flow algorithm is employed to convert an input physical placement into a legal circuit block placement, utilizing a pyramidal network flow algorithm that constructs hierarchical representations and reduces large problems into smaller sub-problems, ensuring minimal displacement and adherence to constraints through a multi-level pyramid approach.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If geometric sorting methods are used for circuit block legalization, then the placement process is simple, but the accuracy is poor and displacement is not minimized effectively
Solution Approach 1:
The patent divides the large-scale circuit placement problem into hierarchical levels (coarse placement, intermediate placement, fine placement). Each level handles a different scale and precision requirement, allowing the system to achieve both computational efficiency and high accuracy by solving smaller sub-problems at each level rather than attempting to solve the entire problem at once.
Solution Approach 2:
The patent introduces a hierarchical dimension to the placement problem, transforming it from a single-level 2D placement task into a multi-level 3D problem (adding the hierarchy level as a third dimension). This allows the system to manage complexity by operating at different scales simultaneously, achieving both simplicity and precision.
2Reliability
If flat graph-based approaches are used for circuit block legalization, then the method is comprehensive, but the runtime is slow and computationally expensive
Solution Approach 1:
The patent segments the comprehensive constraint satisfaction problem into multiple hierarchical levels, where each level handles a subset of constraints and placement decisions. This segmentation reduces the computational burden at each level while maintaining overall completeness through the hierarchical structure.
Solution Approach 2:
The patent applies partial action by addressing constraints hierarchically - coarse placement handles global density constraints first, then intermediate placement addresses regional constraints, and fine placement handles local constraints. This partial approach at each level collectively achieves complete constraint satisfaction without the computational cost of handling all constraints simultaneously.
3Productivity
If multi-level pyramidal approach is used for circuit block legalization, then speed and accuracy are improved, but the algorithm complexity increases
Solution Approach 1:
The patent segments the complex algorithm into standardized hierarchical levels with clear interfaces between them. Each level has well-defined input/output formats and constraint handling rules, which reduces the perceived complexity by providing a structured framework that can be implemented systematically.
Solution Approach 2:
The patent implements dynamic refinement where the placement solution evolves from coarse to fine levels. The algorithm adapts the level of detail and constraint strictness at each hierarchical level, allowing simpler processing at higher levels and more detailed processing at lower levels, which manages complexity through dynamic adjustment of processing intensity.
Data Source
AI summary
A circuit design system is configured to generate a circuit design for an integrated circuit. The circuit design system includes a placement tool configured to generate a graph comprising flows between objects in a first level of a pyramid and targets in the first level. The placement tool generates clusters of objects in a second level of the pyramid in each of the objects in the first level. The objects in the first and the second levels comprise circuit blocks in the circuit design. The placement tool generates clusters of targets in the second level of the pyramid in each of the targets in the first level. The targets in the first and the second levels include subregions of the integrated circuit. The placement tool generates flows from the objects in the second level to the targets in the second level for a placement of the circuit blocks.