Pyramidal Silicon Substrates for Low-Defect Heteroepitaxy

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Solution Overview

Problem

Heterogeneous epitaxy on silicon wafers often results in high defect densities due to lattice mismatch between germanium or III-V compounds and silicon, leading to threading dislocations that can hinder the development of efficient CMOS nodes.

Innovation Solution

The formation of silicon pyramids with (111) sidewalls on the silicon substrate, which act as recesses for epitaxial layer growth, traps threading dislocations and reduces defect densities by providing a lattice-mismatched environment for epitaxial layer deposition, allowing for the growth of defect-free epitaxial layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If heterogeneous epitaxy is performed directly on silicon substrate, then germanium or III-V compounds can be grown for high-speed devices, but threading dislocations and high defect densities occur due to lattice mismatch

Engineering Contradiction:
Improvegrowth of high-speed semiconductor devicesVSAvoiddefect density
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the epitaxial growth process into two distinct stages: first growing a strain-relax buffer layer to accommodate lattice mismatch, then growing the final device layer on top of this buffer. This segmentation allows the system to handle the lattice mismatch problem systematically, preventing threading dislocations from propagating into the device layer while still enabling heterogeneous epitaxy on silicon.

Inventive Principle:
Principle #1Segmentation

2Reliability

If strain-relax buffer is used to reduce defect density, then threading dislocations are reduced, but buffer layer thickness must be increased

Engineering Contradiction:
Improvedefect densityVSAvoidbuffer layer thickness
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent employs parameter changes by carefully controlling the composition gradient in the strain-relax buffer layer. By gradually changing the germanium or III-V compound concentration rather than using a sudden interface, the buffer can achieve sufficient strain relaxation with reduced thickness, minimizing threading dislocations while avoiding excessive buffer layer thickness that would increase manufacturing complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the growth of defect-free epitaxial layers on silicon wafers, reducing the thickness requirement of strain-relax buffers and improving the quality of subsequent semiconductor devices like transistors.

Implementation Method 1

lattice mismatch between germanium or III-V compounds and silicon, leading to threading dislocations

Methodology Applied
Scientific EffectLattice mismatch:

Implementation Method 2

heterogeneous epitaxy directly on silicon, for example, a strain-relax-buffer

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS11908922B2Heterogeneous semiconductor device substrates with high quality epitaxy
Publication Date: 2024.02.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11908922B2 patent drawing
  • US11908922B2 patent drawing
  • US11908922B2 patent drawing

AI summary

A semiconductor structure includes a substrate, a first epitaxial layer, a second epitaxial layer, and a transistor. The substrate includes a first pyramid protrusion, a second pyramid protrusion, a third pyramid protrusion, and a fourth pyramid protrusion. The first and second pyramid protrusions are arranged along a first direction, the second and fourth pyramid protrusions are arranged along the first direction, and the first and third pyramid protrusions are arranged along a second direction crossing the first direction. The first epitaxial layer is over the substrate and in contact with the first, second, third, and fourth pyramid protrusions. The second epitaxial layer is over the first epitaxial layer. The transistor is over the second epitaxial layer.