Processing Element Q-Value Multiplexing for Scalable Reinforcement Learning
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Solution Overview
Problem
Existing processor architectures for reinforcement learning, such as Q-learning, face challenges in scalability and complexity when handling a high number of Q-value computations, leading to increased design complexity and hardware requirements.
Innovation Solution
A processing element architecture that incorporates a receiving module, computing module, and time-division multiplexing module to efficiently compute and replace Q-values for different dimensions, allowing for scalable reinforcement learning operations with reduced hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor architecture is designed to handle a higher number of Q-value computations, then the processing capability is improved, but the device complexity and hardware area increase
Solution Approach 1:
The processor architecture is divided into multiple processing elements (PEs), each capable of independent Q-value computations. Each PE is further segmented into functional modules including computing modules for Q-value calculation, storage modules for storing Q-values, and time-division multiplexing modules for managing data flow between different dimensions. This segmentation allows the system to handle higher computation loads by distributing work across multiple simpler units rather than requiring one complex processor.
Solution Approach 2:
The patent introduces time-division multiplexing to add a temporal dimension to the data flow architecture. Q-values from different dimensions (e.g., different state-action pairs) are processed in alternating time slots, allowing the same physical hardware resources to serve multiple logical functions. This dimensional approach enables the system to scale computation capacity without proportionally increasing hardware complexity, as time multiplexing allows reuse of existing resources.
2Productivity
If the processor architecture is designed to handle a higher number of Q-value computations, then the processing capability is improved, but the hardware area increases
Solution Approach 1:
Each processing element is designed as a universal unit capable of handling Q-value computations for multiple dimensions through time-division multiplexing. The same computing module, storage module, and data flow paths are reused across different time slots and dimensions, eliminating the need for dedicated hardware for each Q-value computation channel. This multi-functionality allows the processor to scale its effective computation capacity without proportionally increasing the physical hardware area.
Solution Approach 2:
The time-division multiplexing module implements periodic action by alternating between processing Q-values from different dimensions in sequential time slots. Instead of requiring simultaneous processing resources for all dimensions, the system periodically switches between dimension processing, allowing the same hardware resources to be reused in a cyclic manner. This periodic operation enables higher computational throughput within the same hardware area by maximizing resource utilization over time.
Data Source
AI summary
A method of reinforcement learning in a processing element, the method including receiving, by a receiving module, one reward. Further, a computing module computes a Q-value for a first dimension at time tn, based on the reward. The Q-value is locally stored. A time-division multiplexing module replaces the computed Q-value for the first dimension with at least one Q-value computed for a second dimension at time tn+1. The second dimension is different than the first dimension.


