Q2S Mapping Table for QLC Write Amplification Control
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Solution Overview
Problem
Existing memory sub-systems using quad-level cell (QLC) memory face challenges with increased write amplification and performance degradation due to constant updates in logical-to-physical (L2P) mapping tables during the copyback process, and the need for asynchronous power loss protection through intermediate single-level cell (SLC) storage.
Innovation Solution
Implementing a quad-to-single (Q2S) mapping table that maintains a bit flag and linked list for SLCs associated with QLCs, allowing data access from SLCs until QLCs are fully programmed, reducing the need for frequent L2P table updates and minimizing performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If QLC memory is used to increase storage capacity, then storage density is improved, but write amplification increases and performance degrades
Solution Approach 1:
The patent segments the L2P mapping table into two separate tables: a QLC L2P mapping table for quad-level cell mappings and an SLC L2P mapping table for single-level cell mappings. This segmentation allows independent management of mapping updates for each cell type, reducing write amplification on the QLC table while maintaining high storage density through QLC usage.
2Reliability
If L2P mapping table updates are performed frequently during copyback, then data integrity is maintained, but performance degradation increases
Solution Approach 1:
The patent introduces an intermediary SLC buffer between the host and QLC memory. During copyback operations, data is first written to the SLC buffer, and the QLC L2P mapping table is updated only once when the copyback is complete, rather than updating after each intermediate step. This intermediary approach maintains data integrity while significantly reducing the frequency of QLC table updates and associated performance degradation.
3Reliability
If SLC is used for asynchronous power loss protection, then data safety is improved, but device complexity increases
Solution Approach 1:
The patent makes the SLC buffer serve multiple functions: it acts as a temporary storage buffer during copyback operations, provides asynchronous power loss protection, and maintains mapping information in the SLC L2P table. By making the SLC component multi-functional, the patent achieves power loss protection without adding separate dedicated structures, thereby limiting the increase in device complexity.
Data Source
AI summary
Quad-to-single (Q2S) data structure comprising a plurality of entries maintained on a volatile memory device. Each Q2S mapping entry, identified by a physical address of a quad-level cell (QLC) block stripe of a non-volatile memory device, comprises a bit flag and a pointer to a linked list on the volatile memory device. Responsive to programming at least one single-level cell (SLC) block stripe of a plurality of SLC block stripes with data to be programmed to a QLC block stripe, an entry for an identification of the QLC block stripe to be programmed and an entry for each physical address of the at least one SLC block stripe of the plurality of SLC block stripes programmed with data to be programmed to the QLC block stripe is appended to a linked list corresponding to a Q2S mapping entry associated with the QLC block stripe to be programmed.