Q2S Mapping Table for QLC Copyback Without Frequent L2P Updates
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Solution Overview
Problem
Existing memory sub-systems using quad-level cell (QLC) memory face challenges with increased write amplification and performance degradation due to frequent updates in logical-to-physical (L2P) mapping tables during the copyback process from single-level cell (SLC) cache to QLC, and the need for asynchronous power loss protection.
Innovation Solution
Implementing a quad-to-single (Q2S) mapping table that maintains a bit flag and linked list for SLCs associated with each QLC, allowing data access from SLCs until QLC is fully programmed, reducing the frequency of L2P table updates and minimizing performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent updates are made to L2P mapping tables during copyback process, then data consistency is maintained, but write amplification increases and performance degrades
Solution Approach 1:
The mapping table is segmented into two separate structures: L2P mapping table for logical-to-physical address translation, and Q2S mapping table for tracking quad-level cell programming status. This segmentation allows independent management of each mapping function, reducing the frequency and impact of updates to the main L2P table while maintaining data consistency through the specialized Q2S table.
Solution Approach 2:
The Q2S mapping table acts as an intermediary structure between the host system and the physical memory cells. It mediates address translation requests by first checking programming status, then directing to appropriate SLC or QLC locations. This intermediary layer reduces direct updates to the main L2P table, thereby reducing write amplification and performance degradation.
2Measurement precision
If L2P mapping table is updated frequently during copyback, then programming status is tracked accurately, but device complexity and update overhead increase
Solution Approach 1:
The mapping functionality is segmented into two specialized tables: L2P for address translation and Q2S for programming status tracking. Each table has a specific purpose and update pattern, which simplifies the management logic compared to a single monolithic mapping table that must handle both functions simultaneously.
Solution Approach 2:
The Q2S mapping table maintains its own update protocol independent of the main L2P table. It self-manages the tracking of programming status through bit flags and linked lists, reducing the computational overhead and complexity of coordinating updates across a single unified mapping structure.
3Speed
If SLC cache is used for data storage, then read performance is improved, but write amplification increases due to additional copyback operations
Solution Approach 1:
The system dynamically determines the source of data (SLC or QLC) based on the programming status stored in the Q2S mapping table. This dynamic approach allows the system to optimize between using fast SLC cache when QLC is not ready, and using capacity-efficient QLC when fully programmed, thereby reducing unnecessary copyback operations and write amplification.
Solution Approach 2:
The Q2S mapping table provides feedback information about the programming status of QLC blocks. This feedback mechanism allows the system to make informed decisions about whether to service read requests from SLC or QLC, optimizing the balance between read performance and write amplification without excessive copyback operations.
Data Source
AI summary
Quad-to-single (Q2S) data structure comprising a plurality of entries maintained on a volatile memory device. Each Q2S mapping entry, identified by a physical address of a quad-level cell (QLC) block stripe of a non-volatile memory device, comprises a bit flag and a pointer to a linked list on the volatile memory device. Responsive to programming at least one single-level cell (SLC) block stripe of a plurality of SLC block stripes with data to be programmed to a QLC block stripe, an entry for an identification of the QLC block stripe to be programmed and an entry for each physical address of the at least one SLC block stripe of the plurality of SLC block stripes programmed with data to be programmed to the QLC block stripe is appended to a linked list corresponding to a Q2S mapping entry associated with the QLC block stripe to be programmed.