QAM Multiband TSV Link Phase Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional chip-to-chip communication methods face challenges in achieving high bandwidth without increasing clock rates or I/O connections, particularly in 3D integrated circuits, and existing phase synchronization techniques for RF communications are power-intensive and have high latency due to reliance on digital signal processing.
Innovation Solution
A phase synchronization method that uses predefined signal patterns and digital codes to adjust the phase delay of a phase-locked loop (PLL) for modulation and demodulation, eliminating the need for digital signal processing and reducing latency and power consumption by utilizing a phase adjustment controller to maximize signal strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If digital signal processing is used for phase synchronization in RF communications, then phase tuning flexibility is improved, but power consumption increases and latency increases
Solution Approach 1:
The phase synchronization function is segmented into two parts: a calibration phase that performs comprehensive phase tuning using predefined patterns, and an operational phase that uses the calibrated settings. This segmentation allows flexible phase tuning during calibration while avoiding continuous high power consumption during normal operation.
Solution Approach 2:
Phase synchronization calibration is performed preliminarily using predefined signal patterns before actual data transmission. The phase adjustment controller determines optimal phase settings in advance, storing them for subsequent operations. This preliminary action achieves flexible phase tuning while reducing ongoing power consumption during data transmission.
2Adaptability or versatility
If digital signal processing is used for phase synchronization, then phase tuning capability is improved, but circuit complexity increases
Solution Approach 1:
The system segments phase synchronization into a calibration mode using predefined patterns and a normal operation mode. During calibration, the phase adjustment controller systematically adjusts phase across multiple cycles using simple pattern matching, avoiding the need for complex continuous DSP circuitry while achieving comprehensive phase tuning capability.
Solution Approach 2:
Instead of using complex DSP circuitry for continuous phase adjustment, the system creates a copy of the transmitted predefined pattern at the receiver and compares it with the received signal. This simple pattern copying and comparison approach achieves accurate phase synchronization without requiring complex processing circuits.
3Productivity
If more TSVs are used to increase I/O connections for higher bandwidth, then communication bandwidth is improved, but manufacturing cost increases and substrate thinning occurs
Solution Approach 1:
The system changes the parameter of signal frequency by implementing multiband modulation, allowing communication to occur across multiple frequency bands simultaneously. This parameter change enables higher effective bandwidth through existing TSV connections without requiring additional physical I/O connections, thereby avoiding increased manufacturing costs and substrate thinning issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient phase synchronization with reduced latency and power consumption, suitable for short-range chip-to-chip communications, particularly in 3D integrated circuits, while maintaining high interference tolerance and scalability.
Implementation Method 1
a phase adjustment controller...controlling phase of a phase locked loop (PLL) circuit coupled to multiple-frequency mixers in said demodulation circuit
Data Source
AI summary
A chip-to-chip communications circuit which is particularly well-suited for short range wired RF communication from one integrated circuit (chip) to another is presented. The circuits preferably utilize multi-frequency quadrature amplitude modulation (QAM) mechanisms for converting digital data bits from a parallel form into a serial analog stream for communication over a chip I/O connection. During a phase calibration cycle, a phase adjustment controller in the transmitter interoperates with a phase adjustment controller in the receiver, to adjust a phase locked-loop (PLL) circuit to correct for the phase delay arising in response to signal propagation between transmitter and receiver.