QC-DBTC Variable-Rate FEC Encoding for High-Rate Wireless Links
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Solution Overview
Problem
Current wireless data communication systems lack an efficient method for generating and decoding Forward Error Correction (FEC) codes with variable rates, particularly in high-rate wireless data systems, which limits their adaptability to changing channel conditions and packet sizes.
Innovation Solution
The development of an apparatus and method for generating and decoding Quasi-Complementary Duo-Binary Turbo Codes (QC-DBTC) that allows for various code rates and adaptability to different channel states, buffer states, and transmission durations, using a duo-binary turbo encoder with quad-symbol mapping and interleaving to optimize FEC performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed-rate FEC codes are used in wireless data communication systems, then the system structure is simple and easy to implement, but the adaptability to changing channel conditions and packet sizes is poor
Solution Approach 1:
The patent implements dynamic code rate selection by enabling the FEC encoder to switch between different code rates (1/2, 2/3, 3/4, etc.) based on channel conditions and packet sizes. The system dynamically adjusts the number of parity bits generated relative to information bits, allowing adaptive optimization of error correction performance for varying transmission conditions without requiring multiple fixed-rate code structures
Solution Approach 2:
The patent changes the code rate parameter of the FEC code to adapt to different channel conditions and packet sizes. By varying the code rate (the ratio of information bits to total coded bits), the system can optimize transmission reliability for good channels (higher code rates) and error-prone channels (lower code rates), while also matching different packet size requirements
2Adaptability or versatility
If variable-rate FEC codes are implemented to adapt to different channel states and packet sizes, then the adaptability improves, but the system complexity and implementation difficulty increase
Solution Approach 1:
The patent implements dynamic code rate adaptation in both encoding and decoding. The encoder can select from multiple code rates (1/2, 2/3, 3/4, etc.) based on packet size and channel conditions, and the decoder is configured to handle variable-rate codes by adjusting its processing accordingly. This dynamic capability allows the system to match code rates to specific packet sizes and channel states while maintaining manageable complexity through systematic design
Solution Approach 2:
The patent varies the code rate parameter to match different packet sizes and channel conditions. By changing the ratio of information bits to parity bits, the system can optimize performance for various packet lengths and error conditions, while the structured approach to variable-rate implementation keeps complexity controlled
3Productivity
If conventional FEC encoding is used, then the implementation is straightforward, but the transmission efficiency and error correction performance are limited
Solution Approach 1:
The patent segments the FEC encoding process into distinct functional blocks: information bit input, parity bit generation, interleaving, and mapping to transmission symbols. This segmentation allows each component to be optimized independently - the interleaver can be designed for maximum error correction performance, and the mapper can be optimized for transmission efficiency - while maintaining overall system manageability through modular architecture
Solution Approach 2:
The patent introduces an interleaver as an intermediary component between the FEC encoder and the transmission mapper. This interleaver acts as a mediator that rearranges the coded bits to optimize error correction performance by distributing burst errors across multiple code symbols, thereby improving overall transmission efficiency and reliability without requiring complex encoding algorithms
Data Source
AI summary
An apparatus for generating Quasi-Complementary Duo-Binary Turbo Codes (QC-DBTC). The apparatus includes a QC-DBTC encoder which receives an information symbol stream and generates a plurality of systematic symbol streams and a plurality of parity symbol streams according to a given code rate. The apparatus further includes a quad-symbol mapper which quad-maps the systematic symbol streams to one symbol stream, a channel interleaver which independently interleaves the quad-mapped systematic symbol stream and the parity symbol streams, quad-demaps the quad-mapped systematic symbol stream, interlaces symbols in parity symbol streams, and serial-concatenates the quad-demapped systematic symbol stream to the interlaced parity symbol streams. A duo-binary turbo code generator is further provided to repeat the serial-concatenated symbol stream, and select a predetermined number of symbols from the repeated symbol stream according to a code rate and selection information, thereby generating QC-DBTC codes.