QC G-LDPC Encoder Layout for Parallel Parity Processing
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Solution Overview
Problem
Existing G-LDPC codes face limitations in parallel processing due to connections between super check nodes, which restrict the parallelization of unit operations, especially when dealing with large amounts of data, leading to increased computation time and resources required for encoding.
Innovation Solution
The implementation of a G-LDPC encoder with a quasi-cyclic (QC) structure that activates only a portion of super check nodes, allowing each GC encoder to perform independent operations, thereby enabling parallel processing of encoding operations across multiple logic circuits and improving parallel processing performance without increasing the code rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all super check nodes are activated in G-LDPC encoding, then error correction capability is improved, but parallel processing performance deteriorates due to connections between super check nodes
Solution Approach 1:
The patent segments the super check nodes into multiple groups, where each group operates independently on disjoint sets of variable nodes. This segmentation allows parallel processing of encoding operations across multiple logic circuits while maintaining the error correction capability through distributed parity check operations.
Solution Approach 2:
The patent activates only a portion of super check nodes in each encoding operation, specifically selecting super check nodes that correspond to identity matrix blocks in the quasi-cyclic structure. This partial activation achieves sufficient error correction while enabling parallel processing, avoiding the need to activate all super check nodes simultaneously.
2Reliability
If G-LDPC encoding is performed with full super check node activation, then data reliability is improved, but computation time increases
Solution Approach 1:
By segmenting super check nodes into independent groups that operate on disjoint variable node sets, the patent enables simultaneous execution of multiple encoding operations, thereby reducing total computation time while maintaining comprehensive error correction coverage across all data bits.
Solution Approach 2:
The patent performs partial activation of super check nodes in a systematic manner across multiple encoding stages, ensuring that all necessary parity checks are eventually performed without requiring all super check nodes to operate simultaneously, thus reducing computation time while preserving data reliability.
3Productivity
If G-LDPC encoding operations are parallelized across multiple logic circuits, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent employs multiple GC encoders that share a common LDPC encoder core, where each GC encoder performs specialized preprocessing on different portions of the input data. This universal architecture allows parallel processing while avoiding complete duplication of all encoding functions, thereby controlling device complexity.
Solution Approach 2:
The patent segments the encoding function into specialized GC encoder modules and a shared LDPC encoder module, with each segment handling specific portions of the work. This functional segmentation enables parallel processing of different data portions while sharing common resources, reducing overall device complexity compared to fully independent encoders.
4Reliability
If the degree of inner parity variable nodes is increased to improve error correction, then reliability is improved, but parallel processing capability deteriorates
Solution Approach 1:
The patent segments the connections between inner parity variable nodes and super check nodes such that each inner parity variable node connects to exactly one active super check node in a given encoding operation. This segmentation maintains the necessary error correction capability through distributed connectivity while enabling parallel processing by eliminating conflicting multi-node connections.
Data Source
Figure 1
Figure 2A~2B
Figure 2C
AI summary
A generalized low-density parity-check (G-LDPC) encoder, including a plurality of generalized constraint (GC) encoders configured to perform a plurality of GC encoding operations in parallel based on a GC code having a quasi-cyclic (QC) structure including information variable nodes, inner parity variable nodes, and super check nodes configured to perform multiple condition checks, wherein each GC encoder of the plurality of GC encoders includes a plurality of first logic circuits configured to perform a GC encoding operation of the plurality of GC encoding operations; and an LDPC encoder configured to perform an LDPC encoding operation based on an LDPC code having the QC structure, wherein the LDPC encoder includes a plurality of single check nodes configured to perform a single parity check, wherein the each GC encoder is configured to receive information bits, and to determine parity bits of a portion of inner parity bits corresponding to the information bits by enabling only a portion of the plurality of first logic circuits to perform the GC encoding operation, and wherein the LDPC encoder is configured to: obtain the inner parity bits by combining the parity bits obtained from the plurality of GC encoders, determine outer parity bits corresponding to the information bits and the inner parity bits by performing the LDPC encoding operation, and output the information bits, the inner parity bits, and the outer parity bits as a codeword.